SY100E137JC Micrel Inc, SY100E137JC Datasheet

SY100E137JC

Manufacturer Part Number

SY100E137JC

Description

IC COUNTER RIPPLE 8-BIT 28-PLCC

Manufacturer

Micrel Inc

Series

100Er

Datasheet

1.SY10E137JZ.pdf (5 pages)

Specifications of SY100E137JC

Logic Type

Binary Counter

Direction

Number Of Elements

Number Of Bits Per Element

Reset

Asynchronous

Timing

Asynchronous/Synchronous

Count Rate

2.2GHz

Trigger Type

Positive Edge

Voltage - Supply

4.2 V ~ 5.5 V

Operating Temperature

0°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

28-LCC (J-Lead)

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

SY100E137JC

Manufacturer:

Micrel Inc

Quantity:

10 000

Current page: 1 of 5
Download datasheet (65Kb)

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

CLK, CLK

A_Start

FEATURES

PIN NAMES

1.8GHz min. count frequency

Extended 100E V

Synchronous and asynchronous enable pins

Differential clock input and data output pins

Asynchronous Master Reset

Internal 75K input pull-down resistors

Available in 28-pin PLCC packge

CCO

–Q

, EN

output for single-ended use

, Q

–Q

Differential Clock Inputs

Differential Q Outputs

Asynchronous Enable Input

Synchronous Enable Inputs

Asynchronous Master Reset

Switching Reference Output

range of –4.2V to –5.5V

to Output

Function

8-BIT RIPPLE

COUNTER

counters. The two least significant bits were designed

with very fast edge rates, while the more significant bits

maintain standard ECLinPS output edge rates. This allows

the counters to operate at very high frequencies, while

maintaining a moderate power dissipation level.

clock generation, as well as for counters in high-

performance ATE time measurement boards.

available to maximize the device's flexibility for various

applications. The asynchronous enable input, A_Start,

when asserted, enables the counter while overriding any

synchronous enable signals. The E137 features XOR'ed

enable inputs, EN

the CLK input. When only one synchronous enable is

asserted, the counter becomes disabled on the next CLK

transition. All outputs remain in the previous state poised

for the other synchronous enable or A_Start to be

asserted in order to re-enable the counter.

both synchronous enables causes the counter to become

enabled on the next transition of the CLK. EN

and CLK edges are coincident. Sufficient delay has been

inserted in the CLK path (to compensate for the XOR

gate delay and the internal D-flip-flop set-up time) to

ensure that the synchronous enable signal is clocked

correctly; hence, the counter is disabled.

the V

CLK input signal. If a single-ended signal is to be used,

the V

bypassed to ground via a 0.01 F capacitor. V

only source/sink 0.5mA; therefore, it should be used as

a switching reference for the E137 only.

pull-down resistor. Therefore, do not leave the differential

CLK inputs open. Doing so causes the current source

transistor of the input clock gate to become saturated,

thus upsetting the internal bias regulators and

jeopardizing the stability of the device.

an all zero state upon assertion.

DESCRIPTION

The SY10/100E137 are very high speed binary ripple

The devices are ideally suited for multiple frequency

Both asynchronous and synchronous enables are

The E137 can also be driven single-endedly utilizing

All input pins left open will be pulled LOW via an input

The asynchronous Master Reset resets the counter to

pin should be connected to the CLK input and

output supply as the voltage reference for the

and EN

, which are synchronous to

Rev.: E

Issue Date: March 2006

SY100E137

SY10E137

SY100E137

Amendment: /0

Asserting

SY10E137

(or EN

can

)

Related parts for SY100E137JC

SY100E137JC Summary of contents

Page 1

Micrel, Inc. FEATURES 1.8GHz min. count frequency Extended 100E V range of –4.2V to –5.5V EE Synchronous and asynchronous enable pins Differential clock input and data output pins V output for single-ended use BB Asynchronous Master Reset Internal 75K input ...

Page 2

... Pb-Free package is recommended for new designs. 2 Operating Package Range Marking Commercial SY10E137JC Commercial SY10E137JC Commercial SY100E137JC Commercial SY100E137JC Commercial SY10E137JZ with Pb-Free bar-line indicator Commercial SY10E137JZ with Pb-Free bar-line indicator Commercial SY100E137JZ with Pb-Free bar-line indicator Commercial SY100E137JZ with Pb-Free bar-line indicator = Electricals only ...

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SY100E137JC Micrel Inc, SY100E137JC Datasheet

SY100E137JC

Specifications of SY100E137JC

Available stocks

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SY100E137JC Summary of contents

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