74ABT16500 Fairchild Semiconductor, 74ABT16500 Datasheet

74ABT16500

Manufacturer Part Number

74ABT16500

Description

18-Bit Universal Bus Transceivers with 3-STATE Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74ABT16500.pdf (9 pages)

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Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

74ABT16500

Manufacturer:

FAIRCHILD/仙童

Quantity:

20 000

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74ABT16500CSSC

74ABT16500CMTD

74ABT16500

18-Bit Universal Bus Transceivers with 3-STATE Outputs

General Description

The ABT16500 18-bit universal bus transceiver combines

D-type latches and D-type flip-flops to allow data flow in

transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the

device operates in the transparent mode when LEAB is

HIGH. When LEAB is LOW, the A data is latched if CLKAB

is held at a HIGH or LOW logic level. If LEAB is LOW, the A

bus data is stored in the latch/flip-flop on the HIGH-to-LOW

transition of CLKAB. Output-enable OEAB is active-high.

When OEAB is HIGH, the outputs are active. When OEAB

is LOW, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, and CLKBA. The output enables are com-

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.

Connection Diagram

Order Number

Pin Assignment for SSOP

Package Number

MS56A

MTD56

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS011581.prf

plementary (OEAB is active HIGH and OEBA is active

LOW).

To ensure the high-impedance state during power up or

power down, OE should be tied to GND through a pulldown

resistor; the minimum value of the resistor is determined by

the current-sourcing capability of the driver.

Features

Function Table

Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,

LEBA, and CLKBA.

Note 2: Output level before the indicated steady-state input conditions

were established.

Note 3: Output level before the indicated steady-state input conditions

were established, provided that CLKAB was LOW before LEAB went LOW.

Combines D-Type latches and D-Type flip-flops for

operation in transparent, latched, or clocked mode

Flow-through architecture optimizes PCB layout

Guaranteed latch-up protection

High impedance glitch free bus loading during entire

power up and power down cycle

Non-destructive hot insertion capability

OEAB

Package Description

LEAB

Inputs

CLKAB

(Note 1)

April 1993

Revised January 1999

www.fairchildsemi.com

Output

(Note 2)

(Note 3)

Related parts for 74ABT16500

74ABT16500 Summary of contents

Page 1

... MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16500CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to CC Ground Pin Input Voltage (Note 5) Input Current (Note 5.0 mA Voltage Applied to Any Output in the ...

Page 4

DC Electrical Characteristics Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW ...

Page 5

AC Operating Requirements Symbol Parameter t (H) Setup Time ( CLKAB S t (H) Hold Time ( CLKAB H t (H) Setup Time ( CLKBA S t (H) ...

Page 6

Skew Symbol Parameter t Pin to Pin Skew OSHL (Note 16) HL Transitions t Pin to Pin Skew OSLH (Note 16) LH Transitions t Duty Cycle PS (Note 17) LH–HL Skew t Pin to Pin Skew OST (Note 16) LH/HL ...

Page 7

AC Loading *Includes jig and probe capacitance. FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide www.fairchildsemi.com Package Number MS56A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE ...

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