74ABT16646 Fairchild Semiconductor, 74ABT16646 Datasheet
74ABT16646
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74ABT16646 Summary of contents
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... MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...
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Function Table Inputs OE DIR CPAB CPBA SAB ...
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Logic Diagram 3 www.fairchildsemi.com ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 5.0 mA Voltage Applied to Any Output in the ...
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DC Electrical Characteristics (SSOP Package) Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V ...
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Extended AC Electrical Characteristics (SSOP Package) Symbol Parameter t Propagation Delay PLH t Clock to Bus PHL t Propagation Delay PLH t Bus to Bus PHL t Progagation Delay PLH t SBA or SAB PHL n ...
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Skew (SOIC Package) Symbol Parameter t Pin to Pin Skew OSHL (Note 15) HL Transitions t Pin to Pin Skew OSLH (Note 15) LH Transitions t Duty Cycle PS (Note 16) LH–HL Skew t Pin to Pin Skew OST (Note ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide www.fairchildsemi.com Package Number MS56A 8 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...