74AC163 STMicroelectronics, 74AC163 Datasheet

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74AC163

Manufacturer Part Number
74AC163
Description
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
The 74AC163 is an advanced high-speed CMOS
SYNCRONOUS
fabricated with sub-micron silicon gate and
double-layer metal wiring C
4 bit binary counter with Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine the
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
HIGH SPEED:
f
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
50 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163
IMPROVED LATCH-UP IMMUNITY
MAX
CC
PLH
OH
NIH
CC
= 8 A(MAX.) at T
| = I
(OPR) = 2V to 6V
= 200MHz (TYP.) at V
= V
t
PHL
OL
NIL
= 24mA (MIN)
= 28 % V
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
PRESETTABLE
A
CC
=25°C
2
(MIN.)
MOS tecnology. It is a
CC
= 5V
COUNTER
ORDER CODES
mode of operation as shown in the Truth Table. A
LOW signal on CLEAR overrides counting and
parallel loading and sets all outputs on LOW state
on the next rising edge of CLOCK. A LOW signal
on
information on Parallel Data inputs to be loaded
into the flip-flop on the next rising edge of CLOCK.
With LOAD and CLEAR HIGH, PE and TE permit
counting when both are HIGH. Conversely, a
LOW signal on either PE and TE inhibits counting.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
LOAD
SOP
DIP
DIP
overrides
74AC163M
74AC163B
TUBE
SOP
counting
74AC163
74AC163MTR
74AC163TTR
and
TSSOP
T & R
allows
1/13

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74AC163 Summary of contents

Page 1

... V (OPR PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 163 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74AC163 is an advanced high-speed CMOS SYNCRONOUS PRESETTABLE fabricated with sub-micron silicon gate and 2 double-layer metal wiring C MOS tecnology bit binary counter with Synchronous Clear. ...

Page 2

... INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS CLEAR LOAD Don’t Care Logic level of data input; CARRY OUT : LOGIC DIAGRAM 2/13 PIN DESCRIPTION PIN No ...

Page 3

... TIMING CHART 74AC163 3/13 ...

Page 4

... ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Ground Current CC GND CC T Storage Temperature stg T Lead Temperature (10 sec) L Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied ...

Page 5

... O I = GND 5 GND 5 1.65 V max OLD 5 3.85 V min OHD Value = 25°C -40 to 85°C -55 to 125°C Typ. Max. Min. Max. Min. 1.5 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 1.5 0.9 0.9 2.25 1.35 1.35 2.75 1.65 1.65 2.99 2.9 2.9 4.49 4.4 4.4 5.49 5.4 5.4 2.46 2.4 3.76 3.7 4.76 4.7 0.002 0.1 0.1 0.001 0.1 0.1 0.001 0.1 0.1 0.36 0.44 0.36 0.44 0.36 0.44 0 -75 74AC163 Unit Max. V 0.9 1.35 V 1.65 V 0.1 0.1 0.1 V 0.5 0.5 0 160 -50 mA 5/13 ...

Page 6

... AC ELECTRICAL CHARACTERISTICS (C Symbol Parameter Propagation Delay 3.3 PLH PHL Time CLOCK Propagation Delay 3.3 PLH PHL Time CLOCK to 5.0 CARRY OUT t t Propagation Delay 3.3 PLH PHL Time TE to CARRY 5.0 OUT t CK pulse Width, 3.3 W (Count) HIGH or 5.0 LOW t CK pulse Width, 3.3 W (Load) HIGH or 5 ...

Page 7

... T OUT WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle) Test Condition (V) Min. 5.0 5 10MHz IN Value = 25°C -40 to 85°C -55 to 125°C Typ. Max. Min. Max. Min. 4 CC(opr 74AC163 Unit Max (per circuit) CC 7/13 ...

Page 8

... WAVEFORM 2: PROPAGATION DELAYS CLEAR MODE (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAYS PRESET MODE (f=1MHz; 50% duty cycle) 8/13 ...

Page 9

... WAVEFORM 4: PROPAGATION DELAYS COUNTABLE MODE (f=1MHz; 50% duty cycle) WAVEFORM 5: PROPAGATION DELAYS CASCADE MODE (f=1MHz; 50% duty cycle) 74AC163 9/13 ...

Page 10

... Plastic DIP-16 (0.25) MECHANICAL DATA DIM. MIN. a1 0. 10/13 mm TYP. MAX. MIN. 0.020 1.65 0.030 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 inch TYP. MAX. 0.065 0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050 P001C ...

Page 11

... MIN. TYP 0 0.35 b1 0. 9.8 E 5.8 e 1.27 e3 8.89 F 3.8 G 4 inch MAX. MIN. TYP. 1.75 0.2 0.004 1.65 0.46 0.013 0.25 0.007 0.019 45 (typ.) 10 0.385 6.2 0.228 0.050 0.350 4.0 0.149 5.3 0.181 1.27 0.019 0.62 8 (max.) 74AC163 MAX. 0.068 0.007 0.064 0.018 0.010 0.393 0.244 0.157 0.208 0.050 0.024 P013H 11/13 ...

Page 12

... DIM. MIN 0.05 A2 0.85 b 0.19 c 0.09 D 4.9 E 6. PIN 1 IDENTIFICATION 1 12/13 TSSOP16 MECHANICAL DATA mm TYP. MAX. 1.1 0.10 0.15 0.9 0.95 0.30 0.20 5 5.1 6.4 6.5 4.4 4.48 0.65 BSC 0.60 0. inch MIN. TYP. MAX. 0.433 0.002 0.004 0.006 0.335 0.354 0.374 0.0075 0.0118 0.0035 0.0079 0.193 0.197 0.201 ...

Page 13

... The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom STMicroelectronics GROUP OF COMPANIES © http://www.st.com 74AC163 13/13 ...

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