74ACTQ823 Fairchild Semiconductor, 74ACTQ823 Datasheet - Page 2

• Manufacturer Part Number: 74ACTQ823
• Description: Quiet Seriesa 9-Bit D-Type Flip-Flop with 3-STATE Outputs
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Functional Description
The ACTQ823 consists of nine D-type edge-triggered flip-
flops. These have 3-STATE outputs for bus systems orga-
nized with inputs and outputs on opposite sides. The buff-
ered clock (CP) and buffered Output Enable (OE) are
common to all flip-flops. The flip-flops will store the state of
their individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH CP transition. With OE
LOW, the contents of the flip-flops are available at the out-
puts. When OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops. In addition to the Clock and Output
Function Table
H
L
X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
LOW Voltage Level
HIGH Voltage Level
Immaterial
OE
H
H
H
H
H
H
L
L
L
L
CLR
H
H
H
H
H
H
X
X
L
L

NC
Z
Inputs
High Impedance
LOW-to-HIGH Transition
No Change
EN
X
X
H
H
L
L
L
L
L
L
CP






X
X
X
X
D
H
H
H
L
X
X
X
X
L
L
2
Enable pins, there are Clear (CLR) and Clock Enable (EN)
pins. These devices are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the
EN is HIGH, the outputs do not change state, regardless of
the data or clock input transitions.
Internal
NC
NC
Q
H
H
H
L
L
L
L
L
Output
NC
O
H
Z
Z
Z
Z
Z
Z
L
L
Function
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load