74AHC164 Philips Semiconductors, 74AHC164 Datasheet - Page 2
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74AHC164
Manufacturer Part Number
74AHC164
Description
8-bit serial-in/parallel-out shift register
Manufacturer
Philips Semiconductors
Datasheet
1.74AHC164.pdf
(20 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74AHC164PW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2000 Aug 15
t
C
f
C
PHL
max
SYMBOL
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from 40 to +85 C and from 40 to +125 C.
I
PD
8-bit serial-in/parallel-out shift register
P
f
f
C
V
i
o
/t
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
(C
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
= supply voltage in Volts.
L
PD
V
amb
propagation delay
input capacitance
maximum clock frequency
power dissipation capacitance
CC
V
CP to Q
MR to Q
2
CC
= 25 C; t
f
2
o
) = sum of outputs;
I
f
= GND to V
i
n
n
+
PARAMETER
r
= t
(C
f
L
3.0 ns.
CC
V
CC
.
2
CC
f
o
) where:
C
V
C
C
I
L
L
L
= V
= 15 pF; V
= 15 pF; V
= 50 pF; f = 1 MHz; notes 1 and 2
2
CC
DESCRIPTION
The 74AHC/AHCT164 shift registers are high-speed
silicon-gate CMOS devices and are pin compatible with
Low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT164 input signals are 8-bit serial
through one of two inputs (D
used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an
unused input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q
is a logical AND of the two data inputs (D
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.
or GND
D
in W).
CONDITIONS
CC
CC
= 5 V
= 5 V
74AHC164; 74AHCT164
sa
or D
4.5
4.0
3
175
48
AHC
Product specification
sb
TYPICAL
); either input can be
sa
3.4
3.5
3
175
51
AHCT
, D
sb
) that
0
ns
ns
pF
MHz
pF
, which
UNIT