74AHC273 Philips Semiconductors, 74AHC273 Datasheet - Page 2

• Manufacturer Part Number: 74AHC273
• Description: Octal D-type flip-flop with reset; positive-edge trigger
• Manufacturer: Philips Semiconductors

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
Ground = 0 V; T
Notes
1. C
2. The condition is V
1999 Sep 01
t
f
C
C
C
PHL
max
Ideal buffer for MOS microcontroller or memory
Common clock and master reset
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt trigger actions
Inputs accepts voltages higher than V
See ‘377’ for clock enable version
See ‘373’ for transparent latch version
See ‘374’ for 3-state version
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from 40 to +85 C and 40 to +125 C.
I
O
PD
Octal D-type flip-flop with reset;
positive-edge trigger
P
f
f
C
V
i
o
/t
SYMBOL
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
(C
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
= supply voltage in Volts.
L
PD
V
CC
V
2
amb
CC
f
2
= 25 C; t
o
propagation delay
maximum clock frequency
input capacitance
output capacitance
power dissipation
capacitance
) = sum of outputs;
I
CP to Q
MR to Q
f
= GND to V
i
+
PARAMETER
(C
r
= t
n
L
n
f
CC
V
3.0 ns.
CC
.
2
CC
f
o
) where:
C
C
V
C
notes 1 and 2
I
L
L
L
= V
= 15 pF; V
= 15 pF; V
= 50 pF; f = 1 MHz;
CONDITIONS
CC
2
or GND
DESCRIPTION
The 74AHC/AHCT273 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
All outputs will be forced LOW independently of clock or
data inputs by a LOW on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
D
CC
CC
in W).
= 5 V
= 5 V
4.2
3.7
120
3.0
4.0
14.0
74AHC273; 74AHCT273
AHC
n
TYPICAL
) of the flip-flop.
4.0
3.9
120
3.0
4.0
18.0
AHCT
Product specification
ns
ns
MHz
pF
pF
pF
UNIT