74ALVC16835 Fairchild Semiconductor, 74ALVC16835 Datasheet
74ALVC16835
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74ALVC16835 Summary of contents
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... Ouputs (O n Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port high impedance state. The 74ALVC16835 is designed for low voltage (1.65V to 3.6V) V applications with I/O capability up to 3.6V. CC The 74ALVC16835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation ...
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Connection Diagram Logic Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input Data Inputs 3-STATE Outputs Connect ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 5) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter f Clock Frequency CLOCK t Pulse Width LE High W CLK High or Low t Setup Time Data Before CLK S Data Before LE CLK High CLK Low t Hold Time Data After CLK H ...
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Characteristics OUT OUT FIGURE 1. Characteristics for Output - Pull Up Driver FIGURE 2. Characteristics for Output - Pull Down Driver I versus versus www.fairchildsemi.com ...
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AC Loading and Waveforms FIGURE 3. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 4. Waveform for Inverting and Non-inverting Functions t ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...