74ALVCH16374 Philips Semiconductors, 74ALVCH16374 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16374
• Description: 2.5V/3.3V 16-bit edge-triggered D-type flip-flop 3-State
• Manufacturer: Philips Semiconductors

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The 74ALVCH16374 is a 16-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-State outputs for bus
oriented applications. Incorporates bus hold data inputs which
eliminate the need for external pull-up or pull-down resistors to hold
unused inputs. The 74ALVCH16374 consists of 2 sections of eight
edge-triggered flip-flops. A clock (CP) input and an output enable
(OE) are provided per 8-bit section.
The flip-flops will store the state of their individual D-inputs that meet
the set-up and hold time requirements on the LOW-to-HIGH CP
transition.
When OE is LOW, the contents of the flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the state of the
flip-flops.
QUICK REFERENCE DATA
GND = 0V; T
NOTE:
ORDERING INFORMATION
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
1998 Jun 18
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
Low inductance multiple V
and ground bounce
Direct interface with TTL levels
All data inputs have bushold
Output drive capability 50 transmission lines @ 85 C
Current drive 24 mA at 3.0 V
16-bit edge-triggered D-type flip-flop (3-State)
t
t
f
f
C
C
C
PHL
MAX
P
f
SYMBOL
o
I
PD
PD
D
= output frequency in MHz; V
= C
/t
/t
PLH
is used to determine the dynamic power dissipation (P
PD
amb
PACKAGES
TM
V
= 25 C; t
CC
flow-through standard pin-out architecture
Propagation delay
CP to Qn
Maximum clock frequency
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip flop
Power dissipation capacitance per flip-flop
2
f
i
g
+ S (C
r
= t
CC
f
L
and ground pins for minimum noise
2.5 ns
PARAMETER
V
CC
y
CC
= supply voltage in V; S (C
2
TEMPERATURE RANGE
f
o
) where: f
–40 C to +85 C
–40 C to +85 C
i
= input frequency in MHz; C
D
in mW):
L
V
V
V
V
V = GND to V
V
CC
CC
CC
CC
I
= GND to V
OUTSIDE NORTH AMERICA
V
CC
= 2.5V, C
= 3.3V, C
= 2.5V
= 3.3V
2
74ALVCH16374 DGG
2
74ALVCH16374 DL
PIN CONFIGURATION
f
o
) = sum of outputs.
L
L
CC
CC
= 30pF
= 50pF
1
1
L
CONDITIONS
= output load capacitance in pF;
GND
GND
GND
GND
1OE
1Q4
1Q5
2Q3
2Q4
2Q6
2Q7
2OE
1Q0
1Q1
1Q2
1Q3
V
1Q6
1Q7
2Q0
2Q1
2Q2
V
2Q5
CC
CC
Outputs disabled
Outputs enabled
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
NORTH AMERICA
ACH16374 DGG
ACH16374 DL
SW00074
74ALVCH16374
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TYPICAL
1CP
1D0
1D1
GND
1D2
1D3
V
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
2D4
2D5
GND
2D6
2D7
2CP
Product specification
CC
CC
300
350
2.3
2.4
5.0
16
10
DWG NUMBER
853-2073 19604
SOT370-1
SOT362-1
UNIT
MHz
MHz
pF
pF
pF
ns
ns