74ALVT16260 Philips Semiconductors, 74ALVT16260 Datasheet - Page 2

• Manufacturer Part Number: 74ALVT16260
• Description: 12-bit to 24-bit multiplexed D-type latches 3-State
• Manufacturer: Philips Semiconductors

FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
Philips Semiconductors
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
1998 Jan 30
ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model
Latch-up protection exceeds 500mA per JEDEC Standard
JESD-17.
Distributed V
switching noise.
Output capability (–32mA I
Bus hold inputs eliminate the need for external pull-up resistors.
5V I/O compatible
Live insertion/extraction permitted
Power-up 3-State
Power-up Reset
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
SYMBOL
SYMBOL
C
I
t
t
C
PLH
PHL
CCZ
OUT
IN
PACKAGES
CC
and GND pin configuration minimizes high-speed
Propagation delay
nAx to nBx
Input capacitance
Output capacitance
Total supply current
OH
, 64mA I
PARAMETER
PARAMETER
nBx to nAx
TEMPERATURE RANGE
OL
).
–40 C to +85 C
–40 C to +85 C
OUTSIDE NORTH AMERICA
2
74ALVT16260 DGG
74ALVT16260 DL
DESCRIPTION
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used
in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications
include multiplexing and/or demultiplexing of address and data
information in microprocessor or bus-interface applications. This
device is alto useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline
Package (SSOP) and 56-pin Thin Shrink Small Outline Package
(TSSOP).
T
amb
V
Outputs disabled
V
I/O
CONDITIONS
= 25 C; GND = 0V
I
C = 50 pF
C
= 0 V or V
= 0 V or 5.0 V
L
= 50 pF
CC
NORTH AMERICA
AV16260 DGG
AV16260 DL
CC
2.5V
100
3.5
3.3
through a pull-up resistor;
4
9
74ALVT16260
TYPICAL
Product specification
DWG NUMBER
853-2046-18918
3.3V
2.8
2.6
80
4
9
SOT371-1
SOT364-1
UNIT
UNIT
ns
ns
pF
pF
A