74AUP2G02 Philips Semiconductors, 74AUP2G02 Datasheet

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74AUP2G02

Manufacturer Part Number
74AUP2G02
Description
Low-power Dual 2-input NOR Gate
Manufacturer
Philips Semiconductors
Datasheet

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1. General description
2. Features
The 74AUP2G02 provides a dual 2-input NOR function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
I
I
I
I
I
I
I
I
I
I
I
CC
74AUP2G02
Low-power dual 2-input NOR gate
Rev. 03 — 11 December 2008
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
N
N
N
N
N
N
N
N
range from 0.8 V to 3.6 V.
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114E Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
circuitry provides partial Power-down mode operation
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
. The I
OFF

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74AUP2G02 Summary of contents

Page 1

... Low-power dual 2-input NOR gate Rev. 03 — 11 December 2008 1. General description The 74AUP2G02 provides a dual 2-input NOR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V This device ensures a very low static and dynamic power consumption across the entire V range from 0 ...

Page 2

... Temperature range Name 74AUP2G02DC +125 C 74AUP2G02GT +125 C 74AUP2G02GD +125 C 74AUP2G02GM +125 C 4. Marking Table 2. Marking codes Type number 74AUP2G02DC 74AUP2G02GT 74AUP2G02GD 74AUP2G02GM 5. Functional diagram 001aah877 Fig 1. Logic symbol 74AUP2G02_3 Product data sheet Description VSSOP8 plastic very thin shrink small outline package ...

Page 3

... Fig 001aaj300 Fig 7. SOT902 Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate 74AUP2G02 GND 001aae472 Transparent top view Pin configuration SOT833-1 (XSON8) ...

Page 4

... +125 C amb derates linearly with 8.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode 0 3 Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate Output Min Max Unit 0.5 +4 [1] 0.5 +4 ...

Page 5

... GND GND GND Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate Min Typ Max ...

Page 6

... 3 0 GND Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate Min Typ Max ...

Page 7

... 3 0 GND GND. CC Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate Min Typ Max ...

Page 8

... Figure Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate +125 C Unit amb amb [1] Min Typ Max Min Max ( 17.0 - ...

Page 9

... Table 9. are typical output voltage levels that occur with the output load. OH Input 0 Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate +125 C Unit amb amb [1] Min Typ Max Min Max ( ...

Page 10

... For measuring propagation delays, set-up and hold times and pulse width R 74AUP2G02_3 Product data sheet DUT R T 10. [ Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate V EXT 001aac521 of the pulse generator EXT PLH PHL ...

Page 11

... A pin 1 index 2.5 scale (1) ( 0.27 0.23 2.1 2.4 0.12 0.5 0.17 0.08 1.9 2.2 REFERENCES JEDEC JEITA MO-187 Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate detail 3.2 0.40 0.21 0.4 0.2 0.13 0.1 3.0 0.15 0.19 EUROPEAN ...

Page 12

... scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA - - - MO-252 Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate 4 ( EUROPEAN ISSUE DATE PROJECTION © NXP B.V. 2008. All rights reserved. SOT833-1 07-11-14 07-12- ...

Page 13

... scale 3.1 0.5 0.15 0.6 0.5 1.5 2.9 0.3 0.4 0.05 REFERENCES JEDEC JEITA - - - Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate detail 0.1 0.05 0.05 0.1 EUROPEAN PROJECTION © NXP B.V. 2008. All rights reserved. SOT996-2 ISSUE DATE 07-12-18 07-12- ...

Page 14

... 1.65 0.35 0.15 0.55 0.5 0.1 1.55 0.25 0.05 REFERENCES JEDEC JEITA MO-255 - - - Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate detail 0.05 0.05 0.05 EUROPEAN PROJECTION © NXP B.V. 2008. All rights reserved. SOT902-1 ISSUE DATE 05-11-25 ...

Page 15

... Modifications: 74AUP2G02_2 20080319 74AUP2G02_1 20060828 74AUP2G02_3 Product data sheet Data sheet status Product data sheet Added type number 74AUP2G02GD (XSON8U package). Product data sheet Product data sheet Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate Change notice Supersedes - ...

Page 16

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 11 December 2008 74AUP2G02 Low-power dual 2-input NOR gate © NXP B.V. 2008. All rights reserved ...

Page 17

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 December 2008 Document identifier: 74AUP2G02_3 All rights reserved. ...

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