MC14017BDR2G ON Semiconductor, MC14017BDR2G Datasheet - Page 6

• Manufacturer Part Number: MC14017BDR2G
• Description: IC DECADE COUNTER/DIVIDER 16SOIC
• Manufacturer: ON Semiconductor
• Series: 4000Br
• Type: Decader

Specifications of MC14017BDR2G

• Logic Type: Counter, Decade
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 10
• Reset: Asynchronous
• Trigger Type: Positive Edge
• Voltage - Supply: 3 V ~ 18 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Counter Type: Decade
• Counting Sequence: Up
• Number Of Circuits: 1
• Logic Family: 14017
• Propagation Delay Time: 1000 ns, 460 ns, 350 ns
• Supply Voltage (max): 18 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Function: Counter/Divider
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 18 V
• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 5
• Logical Function: Counter/Divider
• Operating Supply Voltage (typ): 3.3/5/9/12/15V
• Output Type: Standard
• Package Type: SOIC
• Operating Temp Range: -55C to 125C
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 18V
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count Rate: -
• Timing: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MC14017BDR2G; MC14017BDR2GOSTR

sequential within each stage and from stage to stage, with no dead time (except propagation delay).
CLOCK
CLOCK
ENABLE
RESET
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
C
20 ns
out
t
rem
t
Pcp
CLOCK
PLH
t
PLH
t
PHL
t
PLH
CLOCK
CE
Ncp
Q0 Q1
t
PHL
9 DECODED
t
FIRST STAGE
PLH
OUTPUTS
Figure 4. AC Measurement Definition and Functional Waveforms
MC14017B
50%
RESET
• • •
t
PHL
t
PLH
Q8 Q9
t
PHL
t
PLH
t
THL
10%
t
t
PHL
PHL
t
t
APPLICATIONS INFORMATION
PLH
THL
Figure 3. Counter Expansion
t
PHL
t
PLH
t
TLH
90%
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20 ns
t
t
PHL
t
INTERMEDIATE STAGES
CLOCK
CE
rem
THL
Q0Q1
MC14017B
t
PHL
8 DECODED
OUTPUTS
MC14017B
• • •
RESET
t
6
PLH
t
t
THL
TLH
Q8 Q9
t
PLH
20 ns
t
su
t
TLH
10%
90%
20 ns
t
PLH
t
PHL
t
THL
t
TLH
t
TLH
CLOCK
CE
50%
Q1
t
THL
8 DECODED
t
OUTPUTS
20 ns
MC14017B
LAST STAGE
TLH
• • •
RESET
t
THL
t
t
TLH
TLH
Q8 Q9
20 ns
t
THL
t
PLH
t
THL
90%
10%
t
t
t
PHL
TLH
PHL
t
t
THL
THL
50%
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
OL
V
V
V
V
V
V
V
V
V
V
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
DD
DD
DD
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH