CY7C4211V-15AI Cypress Semiconductor Corp, CY7C4211V-15AI Datasheet - Page 4

• Manufacturer Part Number: CY7C4211V-15AI
• Description: IC SYNC FIFO MEM 512X9 32-TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4211V-15AI

• Function: Synchronous
• Memory Size: 4.6K (512 x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Functional Description
The CY7C42X1V provides four status pins: Empty, Full, Almost Empty,
Almost Full. The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to Empty-7 and
Full-7.
The flags are synchronous, that is, they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle
All configurations are fabricated using an advanced 0.65μ P-Well
CMOS technology. Input ESD protection is greater than 2001 V, and
latch-up is prevented by the use of guard rings.
Architecture
The CY7C42X1V consists of an array of 64 to 8K words of nine
bits each (implemented by a dual-port array of SRAM cells),
a read pointer, a write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF.)
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q
rising edge of RS. In order for the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW. All flags are guaranteed to be valid t
after RS is taken LOW.
Document #: 38-06010 Rev. *E
PAE
PAF
RS
OE
Signal Name
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
Description
(continued)
I/O
0-8
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
I
I
) go LOW t
programmed into the FIFO.
programmed into the FIFO.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
RSF
after the
RSF
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will be
presented on the Q
each rising edge of RCLK while REN1 and REN2 are active.
REN1 and REN2 must set up t
read function. WEN1 and WEN2 must occur t
for it to be a valid write function.
An Output Enable (OE) pin is provided to three-state the Q
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Q
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1) is
LOW, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored is the RAM array sequentially and independently
of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows for depth expansion. If
Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset
(RS=LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK.)
Data is stored in the RAM array sequentially and independently
of any on-going read operation.
Description
0-8
0-8
outputs. New data will be presented on
pins is written into the FIFO on each
ENS
CY7C4201V/4211V
before RCLK for it to be a valid
0-8
outputs after t
ENS
0-8
before WCLK
outputs even
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OE
.
0-8
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