IDT72V85L20PA IDT, Integrated Device Technology Inc, IDT72V85L20PA Datasheet - Page 8

• Manufacturer Part Number: IDT72V85L20PA
• Description: IC FIFO ASYNC DUAL 20NS 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V85L20PA

• Function: Asynchronous
• Memory Size: 72K (4K x 18)
• Access Time: 20ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72V85L20PA; 800-1540; 800-1540-5; 800-1540

USAGE MODES:
Width Expansion
input control signals of multiple FIFOs. Status flags (EF, FF and HF) can be
detected from any one FIFO. Figure 13 demonstrates an 18-bit word width by
using the two FIFOs contained in the IDT72V81/72V82/72V83/72V84/72V85s.
Any word width can be attained by adding FIFOs (Figure 13).
Bidirectional Operation
system capable of Read and Write operations) can be achieved by pairing
IDT72V81/72V82/72V83/72V84/72V85s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
Data Flow-Through
and write flow-through mode. For the read flow-through mode (Figure 17), the
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
Word width may be increased simply by connecting the corresponding
Applications which require data buffering between two systems (each
Two types of flow-through modes are permitted, a read flow-through
Figure 13. Block Diagram of One 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18 FIFO Memory Used in Width Expansion Mode
FULL FLAG (FFA)
DATA
RESET (RS)
WRITE (W)
Figure 12. Block Diagram of One 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 FIFO Used in Single Device Mode
IN
FULL FLAG (FF)
(D)
DATA IN (D)
RESET (RS)
WRITE (W)
18
(HALF-FULL FLAG)
EXPANSION IN (XI)
9
XIA
9
FIFO A
HFA
9
72V81/72V82/72V83
72V81
72V82
72V83
72V84
72V85
A or B
FIFO
(HF)
IDT
72V84/72V85
8
FIFO permits a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (t
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from low-to-high, after which the bus would go into a three-state mode
after t
and then would be asserted.
of a single word of data immediately after reading one word of data from a
full FIFO. The R line causes the FF to be deasserted but the W line being low
causes it to be asserted again in anticipation of a new data word. On the rising
edge of W, the new word is loaded in the FIFO. The W line must be toggled when
FF is not asserted to write new data in the FIFO and to increment the write pointer.
Compound Expansion
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
In the write flow-through mode (Figure 18), the FIFO permits the writing
The two expansion techniques described above can be applied together
RHZ
9
FIFO B
ns. The EF line would have a pulse showing temporary deassertion
HFB
9
XIB
READ (R)
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
9
COMMERCIAL TEMPERATURE RANGE
18
3966 drw 14
DATA
READ (R)
EMPTY FLAG (EFB)
RETRANSMIT (RT)
3966 drw 15
WEF
OUT
+ t
(Q)
FEBRUARY 5, 2009
A
) ns after the rising