CY7C4255-10AC Cypress Semiconductor Corp, CY7C4255-10AC Datasheet - Page 17

IC DEEP SYNC FIFO 8KX18 64LQFP

CY7C4255-10AC

Manufacturer Part Number
CY7C4255-10AC
Description
IC DEEP SYNC FIFO 8KX18 64LQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheets

Specifications of CY7C4255-10AC

Function
Synchronous
Memory Size
144K (8K x 18)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Configuration
Dual
Density
144Kb
Access Time (max)
8ns
Word Size
18b
Organization
8Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
45mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1230

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C4255-10AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C4255-10AC
Manufacturer:
IDT
Quantity:
15
Width Expansion Configuration
The CY7C4255/65 can be expanded in width to provide word
widths greater than 18 in increments of 18. During width ex-
pansion mode all control line inputs are common and all flags
are available. Empty (Full) flags should be created by ANDing
Document #: 38-06004 Rev. *A
FULL FLAG (FF)
Figure 1. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration
DATA IN (D)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
36
18
FF
RESET (RS)
7C4255
7C4265
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
EF
FIRST LOAD (FL)
18
18
the Empty (Full) flags of every FIFO; the PAE and PAF flags
can be detected from any one device. This technique will avoid
reading data from, or writing data to the FIFO that is “stag-
gered” by one clock cycle due to the variations in skew be-
tween RCLK and WCLK. Figure 1 demonstrates a 36-word width
by using two CY7C4255/65s.
FF
RESET (RS)
7C4255
7C4265
EF
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
18
DATA OUT (Q)
EMPTY FLAG (EF)
4255–24
CY7C4255
CY7C4265
Page 17 of 22
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