IDT72255LA10PF IDT, Integrated Device Technology Inc, IDT72255LA10PF Datasheet - Page 7

• Manufacturer Part Number: IDT72255LA10PF
• Description: IC FIFO SUPERSYNC 8KX18 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72255LA10PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Access Time: 10ns
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 8ns
• Word Size: 18b
• Organization: 8Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 80mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72255LA10PF; 800-1499

FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
operation: IDT Standard mode or First Word Fall Through (FWFT) mode.
The selection of which mode will operate is determined during Master Re-
set, by the state of the FWFT/SI input.
will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFO. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
ing on which timing mode is in effect.
IDT STANDARD MODE
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After the
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty flag
(PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 4,097th word for IDT72255LA and 8,193th word for IDT72265LA
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.
Again, if no reads are performed, the PAF will go LOW after (8,192-m)
writes for the IDT72255LA and (16,384-m) writes for the IDT72265LA.
The offset “m” is the full offset value. The default setting for this value is
stated in the footnote of Table 1. This parameter is also user programmable.
See section on Programmable Flag Offset Loading.
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 8,192 writes for the IDT72255LA and
16,384 for the IDT72265LA, respectively.
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
The IDT72255LA/72265LA support two different timing modes of
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
Various signals, both input and output signals operate differently depend-
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
If one continued to write data into the FIFO, and we assumed no read
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
7
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause the
FIFO to become empty. When the last word has been read from the FIFO,
the EF will go LOW inhibiting further read operations. REN is
ignored when the FIFO is empty.
double register-buffered outputs.
Figure 7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the Output
Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the
FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 2. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
operations were taking place, the HF would toggle to LOW once the 4,098th
word for the IDT72255LA and 8,194th word for the IDT72265LA, respec-
tively was written into the FIFO. Continuing to write data into the FIFO will
cause the PAF to go LOW. Again, if no reads are performed, the PAF will
go LOW after (8,193-m) writes for the IDT72255LA and (16,385-m) writes
for the IDT72265LA, where m is the full offset value. The default setting for
this value is stated in the footnote of Table 2.
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 8,193 writes for the IDT72255LA and
16,385 writes for the IDT72265LA, respectively. Note that the additional
word in FWFT mode is due to the capacity of the memory plus output
register.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is ig-
nored when the FIFO is empty.
buffered, and the IR flag output is double register-buffered.
and 12.
If the FIFO is full, the first read operation will cause FF to go HIGH.
When configured in IDT Standard mode, the EF and FF outputs are
Relevant timing diagrams for IDT Standard mode can be found in
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
If one continued to write data into the FIFO, and we assumed no read
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
When configured in FWFT mode, the OR flag output is triple register-
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009