LMX2331A National Semiconductor, LMX2331A Datasheet - Page 16

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LMX2331A

Manufacturer Part Number
LMX2331A
Description
PLLatinum Dual Frequency Synthesizer for RF Personal Communications
Manufacturer
National Semiconductor
Datasheet

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Application Information
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX233xA PLL is shown in Figure 5 .
When a new frequency is loaded, and the RF Icp
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter compo-
nent values for the normal steady state considerations. The
device configuration ensures that as long as a second iden-
FIGURE 4. Open Loop Response Bode Plot
(Continued)
FIGURE 5. Fastlock PLL Architecture
o
bit is set
16
tical damping resistor is wired in appropriately, the loop will
lock faster without any additional stability considerations to
account for. Once locked on the correct frequency, the user
can return the PLL to standard low noise operation by send-
ing a MICROWIRE instruction with the RF Icp
This transition does not affect the charge on the loop filter
capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change be-
tween Fastlock and standard mode.
DS012331-29
DS012331-30
o
bit set low.

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