LMX2485E National Semiconductor, LMX2485E Datasheet - Page 36

• Manufacturer Part Number: LMX2485E
• Description: High Performance Delta-Sigma Low Power Dual PLLatinum Frequency Synthesizers
• Manufacturer: National Semiconductor

www.national.com
Programming Description
2.8 R7 REGISTER
2.8.1 DIV4 -- RF Digital Lock Detect Divide By 4
Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked condition for larger
comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison frequency (it does not apply to the IF
comparison frequency) presented to the digital lock detect circuitry by 4. This enables this circuitry to work at higher comparison
frequencies. It is recommended that this bit be enabled whenever the comparison frequency exceeds 20 MHz and RF digital lock
detect is being used.
2.8.2 IF_RST -- IF PLL Counter Reset
When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a Tri-State condition. This feature
should be disabled for normal operation. Note that a counter reset is applied whenever the chip is powered up via software or CE
pin.
2.8.3 RF_RST -- RF PLL Counter Reset
When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a Tri-State condition. This feature
should be disabled for normal operation. This feature should be disabled for normal operation. Note that a counter reset is applied
whenever the chip is powered up via software or CE pin.
2.8.4 RF_TRI -- RF Charge Pump Tri-State
When this bit is enabled, the RF PLL charge pump is put in a Tri-State condition, but the counters are not reset. This feature is
typically disabled for normal operation.
2.8.5 IF_TRI -- IF Charge Pump Tri-State
When this bit is enabled, the IF PLL charge pump is put in a Tri-State condition, but the counters are not reset. This feature is
typically disabled for normal operation.
REGISTER 23 22 21 20 19 18 17 16 15 14
R7
0 (Default)
0 (Default)
0 (Default)
0 (Default)
RF_RST
RF_TRI
IF_RST
IF_TRI
0
1
1
1
1
0
0
0
0
0
0
0
RF PLL N and R Counters
RF PLL N and R Counters
IF PLL N and R Counters
IF PLL N and R Counters
0
(Continued)
0 DIV4 0
Normal Operation
Normal Operation
Normal Operation
Normal Operation
Normal Operation
Normal Operation
Counter Reset
Counter Reset
13
Data[19:0]
12 11 10 9 8
1
36
0 0 0 IF_RST RF_RST IF_CPT RF_CPT 1
7
6
RF PLL Charge Pump
RF PLL Charge Pump
IF PLL Charge Pump
IF PLL Charge Pump
Normal Operation
Normal Operation
Normal Operation
Normal Operation
5
Tri-State
Tri-State
Tri-State
Tri-State
4
C3 C2 C1 C0
3
2
1
1
1
0
1