HT46R221 Holtek Semiconductor Inc, HT46R221 Datasheet

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HT46R221

Manufacturer Part Number
HT46R221
Description
8-Bit A/D Type MCU
Manufacturer
Holtek Semiconductor Inc
Datasheet
Features
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General Description
The device is an 8-bit high performance RISC-like
microcontroller designed for multiple I/O product appli-
cations. It is particularly suitable for use in products
I
Rev. 1.10
2
C is a trademark of Philips Semiconductors
Operating voltage:
f
f
19 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
8-bit programmable timer/event counter with over-
flow interrupt and 7-stage prescaler
On-chip crystal and RC oscillator
Watchdog Timer
2048´14 program memory ROM
64´8 data memory RAM
Supports PFD for sound generation
HALT function and wake-up feature reduce power
consumption
SYS
SYS
=4MHz: 2.2V~5.5V
=8MHz: 4.5V~5.5V
1
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such as washing machine controllers and home appli-
ances. A HALT feature is included to reduce power con-
sumption.
Up to 0.5ms instruction cycle with 8MHz system clock
at V
6-level subroutine nesting
8 channels 9-bit resolution (8-bit accuracy) A/D con-
verter
1-channel (6+2)/(7+1)-bit PWM output shared with
two I/O lines
Bit manipulation instruction
14-bit table read instruction
63 powerful instructions
All instructions in one or two machine cycles
Low voltage reset function
I
24-pin SKDIP/SOP package
2
C BUS (slave mode)
DD
8-Bit A/D Type MCU
=5V
HT46R22/HT46C22
October 2, 2002

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HT46R221 Summary of contents

Page 1

Features · Operating voltage: f =4MHz: 2.2V~5.5V SYS f =8MHz: 4.5V~5.5V SYS · 19 bidirectional I/O lines (max.) · 1 interrupt input shared with an I/O line · 8-bit programmable timer/event counter with over- flow interrupt and 7-stage prescaler · ...

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Block Diagram Pin Assignment Rev. 1.10 HT46R22/HT46C22 2 October 2, 2002 ...

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Pad Assignment HT46C22 * The IC substrate should be connected to VSS in the PCB layout artwork. Pad Description Pad Name I/O Options PB0/AN0 Bidirectional 8-bit input/output port. Software instructions deter- PB1/AN1 mine the CMOS output, Schmitt trigger input with ...

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Pad Name I/O Options Bidirectional 1-bit input/output port. Software instructions deter- mine the CMOS output, Schmitt trigger input with or without a Pull-high PD0/PWM I/O pull-high resistor (determined by pull-high option: port option). I/O or PWM The PWM output function ...

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Symbol Parameter Input High Voltage for I/O Ports, V IH1 TMR and INT V Input Low Voltage (RES) IL2 V Input High Voltage (RES) IH2 V Low Voltage Reset LVR I I/O Port Sink Current OL I I/O Port Source ...

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Functional Description Execution flow The system clock for the microcontroller is derived from either a crystal oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction ...

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Program memory - ROM The program memory is used to store the program in- structions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 2048 14 bits, addressed by the program counter ...

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Stack register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 6 levels and is neither part of the data nor ...

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Indirect addressing register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed (01H). Reading location 00H itself indirectly will return the re- sult 00H. Writing ...

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All these kinds of interrupts have a wake-up capability interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram ...

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It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. In- terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and ...

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CLR WDT times selection option . If the CLR WDT is selected (i.e. CLRWDT times equal 1), any exe- cution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. ...

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Reset circuit The registers states are summarized in the following table. Reset WDT Time-out Register (Power On) (Normal Operation) TMR xxxx xxxx xxxx xxxx TMRC 00-0 1000 00-0 1000 Program 000H 000H Counter MP -xxx xxxx -uuu uuuu ACC xxxx ...

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Timer/Event Counter A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or the system clock. Using the internal system clock, there is ...

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Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt trig- ger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) ...

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PFD output signal is controlled by PA3 data register only. Writing 1 to PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain The I/O functions of ...

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A (6+2) bits mode PWM cycle is divided into four modu- lation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period (6+2) bit PWM function, the contents of the PWM register is ...

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Label Bits Function (ADCR) ACS0 0 ACS1 1 Defines the analog channel select. ACS2 2 Defines the port B configuration select. PCR0 3 If PCR0, PCR1 and PCR2 are all 0, the PCR1 4 ADC circuit is power off to ...

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When the A/D conversion is completed, the A/D inter- rupt request flag is set. The EOC bit is set to 1 when the START bit is set from Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ...

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I C BUS Serial Interface BUS is implemented in the device. The I C BUS is a bidirectional 2-wire lines. The data line and clock line are implement in SDA pin and SCL pin. The ...

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Set EHI bit of the interrupt control register 1 (INTC1) 2 bit 0 to enable the I C BUS interrupt. Label Bits Function (HSR) HCF is clear to ²0² when one data byte is being transferred, HCF is set ...

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SRW bit The SRW bit means that the master device wants to 2 read from or write to the I C BUS. The slave device check this bit to understand itself transmitter or a receiver. The ...

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Rev. 1.10 HT46R22/HT46C22 23 October 2, 2002 ...

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Rev. 1.10 HT46R22/HT46C22 24 October 2, 2002 ...

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Options The following shows ten kinds of options in the microcontroller. ALL the options must be defined to ensure proper sys- tem function. No. OSC type selection. 1 This option is to decide crystal oscillator is ...

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Application Circuits Rev. 1.10 HT46R22/HT46C22 26 October 2, 2002 ...

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Instruction Set Summary Mnemonic Arithmetic ADD A,[m] Add data memory to ACC ADDM A,[m] Add ACC to data memory ADD A,x Add immediate data to ACC ADC A,[m] Add data memory to ACC with carry ADCM A,[m] Add ACC to ...

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Mnemonic Branch Jump unconditionally JMP addr SZ [m] Skip if data memory is zero SZA [m] Skip if data memory is zero with data movement to ACC SZ [m].i Skip if bit i of data memory is zero SNZ [m].i ...

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Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simulta- neously, leaving the result in the accumulator. Operation ACC ACC+[m]+C Affected flag(s) ...

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AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND opera- tion. The result is stored in the accumulator. Operation ACC ACC AND [m] Affected flag(s) TC2 TC1 ...

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CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. Operation [m].i 0 Affected flag(s) TC2 TC1 CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). ...

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CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result ...

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HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and ...

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MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. Operation ACC x Affected flag(s) TC2 TC1 MOV [m],A Move the accumulator to data memory Description The contents of ...

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RET Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Operation PC Stack Affected flag(s) TC2 TC1 RET A,x Return and place immediate data in the accumulator Description The program counter is ...

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RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re- places the carry bit; the original carry flag is rotated into the ...

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RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is ...

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SET [m] Set data memory Description Each bit of the specified data memory is set to 1. Operation [m] FFH Affected flag(s) TC2 TC1 SET [m]. i Set bit of data memory Description Bit i of the specified data memory ...

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SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the re- sult in the accumulator. Operation ACC ACC+[m]+1 Affected flag(s) TC2 TC1 SUBM A,[m] Subtract data memory ...

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SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper ...

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XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu- sive_OR operation and the result is stored in the accumulator. Operation ACC ACC XOR [m] Affected flag(s) ...

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Package Information 24-pin SKDIP (300mil) outline dimensions Symbol Min. A 1235 B 255 C 125 D 125 295 I 345 0 Rev. 1.10 HT46R22/HT46C22 Dimensions in mil Nom. Max. 1265 265 135 145 20 ...

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SOP (300mil) outline dimensions Symbol Min. A 394 B 290 590 Rev. 1.10 HT46R22/HT46C22 Dimensions in mil Nom. Max. 419 300 20 614 104 50 38 ...

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Product Tape and Reel Specifications Reel dimensions SOP 24W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 HT46R22/HT46C22 Dimensions in mm ...

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Carrier tape dimensions SOP 24W Symbol Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 ...

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... Fax: 510-252-9885 http://www.holmate.com Copyright 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise ...

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