HT46C62 Holtek Semiconductor, HT46C62 Datasheet - Page 14

• Manufacturer Part Number: HT46C62
• Description: A/D with LCD Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

Real Time Clock - RTC
The real time clock (RTC) is operated in the same man-
ner as the time base that is used to supply a regular in-
ternal interrupt. Its time-out period ranges from f
f
RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 6 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a sub-
routine call to location 18H occurs.
Note: * not recommended to be used
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following.
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port A, or
a WDT overflow. An external reset causes device initial-
ization, and the WDT overflow performs a warm reset .
After examining the TO and PDF flags, the reason for
chip reset can be determined. The PDF flag is cleared by
system power-up or by executing the CLR WDT in-
Rev. 1.60
S
/2
The system oscillator turns off but the WDT oscillator
keeps running (if the WDT oscillator or the real time
clock is selected).
The contents of the on-chip RAM and of the registers
remain unchanged.
The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time
clock oscillator).
All I/O ports maintain their original status.
The PDF flag is set but the TO flag is cleared.
LCD driver is still running
(if the WDT OSC or RTC OSC is selected).
RT2
15
0
0
0
0
1
1
1
1
by software programming. Writing data to RT2,
RT1
0
0
1
1
0
0
1
1
RT0
0
1
0
1
0
1
0
1
RTC Clock Divided Factor
2
2
2
2
2
2
2
2
10
11
8
9
12
13
14
15
*
*
*
*
S
Real Time Clock
/2
8
to
14
struction, and is set by executing the HALT instruction.
On the other hand, the TO flag is set if WDT time-out oc-
curs, and causes a wake-up that only resets the program
counter and SP, and leaves the others at their original
state.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the in-
terrupt is enabled, and the stack is not full, the regular in-
terrupt response takes place.
When an interrupt request flag is set before entering the
that interrupt.
If wake-up events occur, it takes 1024 t
clock period) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which reset may occur.
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a warm reset that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the initial condition once the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
HALT status, the system cannot be awakened using
chip resets .
RES is reset during normal operation
RES is reset during HALT
WDT time-out is reset during normal operation
HT46R62/HT46C62
July 14, 2005
SYS
(system