HT68F04 Holtek Semiconductor, HT68F04 Datasheet - Page 35
HT68F04
Manufacturer Part Number
HT68F04
Description
Small Package Enhanced Flash Type 8-Bit MCU
Manufacturer
Holtek Semiconductor
Datasheet
1.HT68F04.pdf
(139 pages)
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SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses either the LXT or LIRC
low speed system oscillator. To switch back to the
NORMAL Mode, where the high speed system oscillator
is used, the HLCLK bit should be set to ²1² or HLCLK bit
is ²0², but CKS2~CKS0 is set to ²010², ²011², ²100²,
²101², ²110² or ²111². As a certain amount of time will be
required for the high frequency clock to stabilise, the
status of the HTO bit is checked. The amount of time
required for high speed system oscillator stabilization
depends upon which high speed system oscillator type
is used.
Rev. 1.00
HT66F03/HT66F04/HT68F03/HT68F04
35
Entering the SLEEP0 Mode
There is only one way for the device to enter the
SLEEP0 Mode and that is to execute the ²HALT² instruc-
tion in the application program with the IDLEN bit in
SMOD register equal to ²0² and the WDT and LVD both
off. When this instruction is executed under the condi-
tions described above, the following will occur:
·
·
·
·
·
The system clock, WDT clock and Time Base clock
will be stopped and the application program will stop
at the ²HALT² instruction.
The Data Memory contents and registers will maintain
their present condition.
The WDT will be cleared and stopped no matter if the
WDT clock source originates from the f
from the system clock.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
¹
April 16, 2010
SUB
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