MAS3587F Micronas, MAS3587F Datasheet
MAS3587F
Available stocks
Related parts for MAS3587F
MAS3587F Summary of contents
Page 1
... MICRONAS Edition March 2, 2001 6251-542-1AI ADVANCE INFORMATION MAS 3587F MPEG Layer 3 Audio Encoder/Decoder MICRONAS ...
Page 2
... Firmware and Software 8 2.5.1. Internal Program ROM and Firmware, MPEG-Encoding/Decoding 9 2.5.2. Program Download Feature 9 2.6. Audio Codec 9 2.7. A/D Converter and Microphone Amplifier 9 2.7.1. Baseband Processing 9 2.7.1.1. Bass, Treble, and Loudness 9 2.7.2. Micronas Dynamic Bass (MDB) 9 2.7.2.1. Automatic Volume Control (AVC) 10 2.7.2.2. Balance and Volume 10 2.7.3. D/A Converters 10 2.7.4. Output Amplifiers 10 2.8. Clock Management 11 2.8.1. DSP Clock 11 2.8.2. ...
Page 3
... Pin Connections and Short Descriptions 53 4.3. Pin Descriptions 53 4.3.1. Power Supply Pins 53 4.3.2. Analog Reference Pins 53 4.3.3. DC/DC Converters and Battery Voltage Supervision 53 4.3.4. Oscillator Pins and Clocking 53 4.3.5. Control Lines 53 4.3.6. Parallel Interface Lines Micronas ) hex ) hex ) hex ) hex ) hex ) hex ) hex ) hex ) hex ) hex ) hex MAS 3587F ...
Page 4
... S/PDIF Input Characteristics 69 4.6.3.5. S/PDIF Output Characteristics 70 4.6.3.6. PIO as Parallel Input Interface: DMA Mode 71 4.6.3.7. PIO as Parallel Output Interface: DMA Mode 72 4.6.4. Analog Characteristics 76 4.6.5. DC/DC Converter Characteristics 77 4.6.6. Typical Performance Characteristics 79 4.7. Typical Application in a Portable Player 80 4.8. Recommended DC/DC Converter Application Circuit 82 5. Data Sheet History 4 ADVANCE INFORMATION Micronas ...
Page 5
... Additional functionality is achieved via download soft- ware (e.g. Micronas SC4 encoder/decoder). SC4 is a proprietary Micronas speech codec technology based on ADPCM. The codec can be downloaded to the MAS 3587F to allow high quality speech recording and playing back at various sampling rates ...
Page 6
... V sup- ply. The performance of the DC/DC converters reaches efficiencies up to 95%. Audio D/A baseband features MP3 Headphone encoding/ amplifier decoding Volume Optional Software Downloads 2 C DC/DC1 e.g. 2 Connector ADVANCE INFORMATION Headphone digital out S/PDIF or serial DC/DC2 e.g. 3 2.2 V Micronas ...
Page 7
... Div. V2 Xtal Osc. 18.432 MHz Fig. 2–1: The MAS 3587F architecture Micronas 2.3. DSP Core The internal processor is a dedicated DSP for advanced audio applications. 2.4. RAM and Registers The DSP core has access to two RAM banks denoted D0 and D1. All RAM addresses can be accessed in a ...
Page 8
... All four factors LL, LR, RL, and RR are adjustable, please refer to Fig. 3–3 on page 41. Encoder MIX DSP Volume Decoder Matrix MIX ADVANCE INFORMATION 2 C instructions that give access to PIO S/PDIF SDO Audio OUT D/A Proc. S/PDIF SDO Audio OUT D/A Proc. Micronas ...
Page 9
... Table 3–12 on page 43 for details). 2.7.2. Micronas Dynamic Bass (MDB) on The Micronas Dynamic Bass system (MDB) was developed to extend the frequency range of loud- speakers or headphones below the cutoff frequency of the speakers. In addition to dynamically amplifying the low frequency bass signals, the MDB exploits the psy- choacoustic phenomenon of the ‘ ...
Page 10
... The volume range is 114...+12 dB with an addi- tional mute position. A balance function is provided (see Table 3–12 on page 43). 2.7.3. D/A Converters A pair of Micronas’ unique multibit sigma-delta D/A converters is used to convert the audio data with high linearity and a superior S/N. In order to attenuate high- frequency noise caused by noise-shaping, internal low-pass filters are included ...
Page 11
... Beside these regions, the DC/DC converters have start-up circuits of their own which get their power via pin VSENSx. Micronas 2.9.2. DC/DC Converters The MAS 3587F has two embedded high-performance step-up DC/DC converters with synchronous rectifiers to supply both the DSP core itself and external circuitry such as a controller or flash memory at two different voltage levels. An overview is given in Fig. 2– ...
Page 12
... Fig. 2–7: DC/DC converter overview (DCEN input must be connected to pin I2CVDD via the start-up push button) 12 battery VBAT voltage monitor supply I2CVDD DCSO2 DCSG2 DC/DC converter 2 VSENS2 voltage monitor Start DCEN S PUP R voltage monitor DC/DC converter 1 VSS ADVANCE INFORMATION output 330 Micronas ...
Page 13
... A battery voltage supervision circuit (at pin VBAT) is provided which is independent of the DC/DC convert- ers. It can be programmed to supervise one or two bat- tery cells. The voltage is measured by subsequently setting a series of voltage thresholds and checking the respective comparison result in register 77 Table 3–3 on page 20). Micronas VSENS1 Flash 2 I CVDD C ...
Page 14
... DSP software. The PIO interface is always used for MPEG-data out- put. For the handshake protocol please refer to Section 4.6.3.7. For MPEG-data input, the PIO interface is activated by setting bits 9,8 in D0:7f1 to 01. For the handshake pro- tocol please refer to Section 4.6.3.6. Micronas ...
Page 15
... Micronas MAS 3587F 2.13. Default Operation This sections refers to the standard operation mode ”power-optimized solution” (see Section 2.9.3.). 2.13.1. Stand-by Functions After applying the battery voltage, the system will remain stand-by, as long as the DCEN pin level is kept low ...
Page 16
... ADVANCE INFORMATION ). hex 2 C subaddress 6a ). After hex 2 C. The A/D and the D/A con hex ). The D/A converters may either hex and 00 hex ). Finally, an appropriate hex subaddress 6c ) must hex hex subaddress 6c ). The hex hex ). By clearing both DC/DC hex 2 C subaddress Micronas 2 C ...
Page 17
... C registers of the MAS 3587F are 16 bits wide, the MSB is denoted as bit[15]. Transmissions via I bus have to take place in 16-bit words (two byte trans- fers, MSB sent first); thus, for each register access, two 8-bit data words must be sent/received via I bus. Micronas Table 3–2: I Sub- address (hex) 2 ...
Page 18
... MAS 3587F is processing the I2C command write data to DSP read data from DSP dd dd> and stop with NAK 2 C bus protocols for write and read low data word high data word A low data word (ACK (NAK Start S = Stop P Micronas ...
Page 19
... Read Direct Configuration Register 1) send subaddress DW subaddress get register value DW A subaddress check the PUP1 and PUP2 power-up flags necessary to read back the content of the direct configuration reg- isters. Micronas d3,d2 A d1, d3,d2 A d1, MAS 3587F ...
Page 20
... V (reset) 1.3 V 2.4 ... 3.0 V 1.6 V 3.0 ... 3.6 V reserved reserved enable DC/DC 2 (reset=1) enable DC/DC 1 (reset=1) enable and reset audio codec enable and reset DSP core ). The audio codec hex reset codec reset DSP core reserved, must be set to zero reserved, must be set to zero ADVANCE INFORMATION Name CONTROL Micronas ...
Page 21
... Disable synchronized rectifier 1 0 The DC/DC converters are up-converters only. Thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. 1) refer to Section 4.6.2. on page 59 Micronas ) hex Nominal set level reset level output volt. of PUP2 of PUP2 3 ...
Page 22
... The DC/DC converters are up-converters only. Thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. 22 Pulse frequency modulation (PFM) Pulse width modulation (PWM) (reset) disable synchronized recitifier enable synchronized recitifier (reset) ADVANCE INFORMATION Name Micronas ...
Page 23
... DC/DC converters is directly derived hex from the crystal frequency (nominal 18.432 MHz). Otherwise, the synthesizer clock is used as the reference (please refer to the respective column in Table 2–1 on page 10). Micronas ) hex input voltage at pin VBAT above defined threshold input voltage at pin VBAT below defined threshold 1 cell (range 0 ...
Page 24
... The controller writes an internal register of the MAS 3587F The controller reads a block of the DSP memory The controller reads a block of the DSP memory The controller writes a block of the DSP memory The controller writes a block of the DSP memory ADVANCE INFORMATION 2 C interface peri data 2 C data register, all Micronas ...
Page 25
... In contrast to memory cells, registers cannot be accessed as a block but must always be addressed individually. Example: Read the content of the PIO data register (C8 < 80> <DW 69 < dd> Micronas a3 ,a2 a1, and the respective RAM area has been configured as program RAM ...
Page 26
... The telegram to read 3 words starting at location D0:100 is < 00> <DW 69 < b,r1 r0, d3,d2 A d1, into the register with the number AA ) hex c,0 0 n3,n2 n1, a3,a2 A a1, d3,d2 A d1,d0 W d3,d2 d1, dd> ADVANCE INFORMATION : hex Micronas ...
Page 27
... Read D1 Memory (Code D 1) send command $ get memory value DW $ x,x x,d4 A ...repeat for n data values... x,x x,d4 A The Read D1 Memory command is provided to get information from D1 memory cells of the MAS 3587F. Micronas ) hex c,4 0 n3,n2 n1, a3,a2 a1, d3,d2 A ...
Page 28
... n3,n2 n1, a3,a2 a1, d1, d1, protocol: ) hex e n3,n2 n1, a3,a2 a1, 0,0 0, d3,d2 d1, ...repeat for n data values... 0 d3,d2 A d1, protocol: hex ADVANCE INFORMATION fol- hex Micronas ...
Page 29
... Write D1 Memory (Code For further details, see the Write D0 Memory command. 3.3.1.11. Short Write D1 Memory (Code $ Only the 16 lower bits of each memory cell are written, the upper 4 bits are cleared. Micronas ) hex e,4 0 n3,n2 A n1, a3,a2 A a1, ...
Page 30
... Now Default Read commands can be issued as often as desired: 'HIDXOW 5HDG command <DW 69 <DR 16 bit content of the dd dd> address as defined by the pointer ... and do it again <DW 69 <DR dd dd> hex 5,0 0 d3,d2 d1, hex ADVANCE INFORMATION : hex Micronas ...
Page 31
... D0:1000 to D0:17ff start program execution at < 00> address D0:1000 3.3.1.15. Serial Program Download Program downloads may also be performed via the I ilar command sequence as in the Fast Program Download (stop transfers, Freeze...) applies. Micronas 6,n2 n1, a3,a2 A a1, hex 2 C interface by using the Write D0/1 Memory commands. A sim- ...
Page 32
... The validate bit will be reset automati- cally after the changes have been taken over by the DSP. The status memory cells are used to read the encoder/ decoder status and to get additional MPEG bitstream information. Note: Memory cells not given in the tables must not be written. Micronas ...
Page 33
... Reserved, must be set to zero ... Micronas ) hex 0 lowest bitrate / quality The maximum bitrate is limited to 192 kbit/s, whereas the average bitrate highly depends on the audio source. At the recommanded quality setting and a sampling rate of 44 ...
Page 34
... CRC protection reserved joint stereo reserved single channel disable MS-Stereo encoding enable MS-Stereo encoding bit stream is not copyright protected bit stream is copyright protected bit stream is a copy bit stream is an original none 50/15 s reserved CCITT J.17 ADVANCE INFORMATION Name MPEG 2 22. Micronas ...
Page 35
... May only be set for MPEG 2 encoding. bit[2] Serial data input interface B clock invert (pin SIBC (reset) ... Micronas ) hex do not invert SOC invert SOC no additional delay (reset) additional delay of data related to word strobe SDI input with PLL SDI input without PLL ...
Page 36
... S/PDIF input 1 select S/PDIF input 2 enable S/PDIF output S/PDIF output off (tristate) SDO on SDO off low impedance high impedance use external audio source (SDI) use internal A/D converter as audio source ADVANCE INFORMATION Name All InterfaceControl Micronas ...
Page 37
... D0:7fd Volume output control: left D0:7fe Volume output control: right D0:7ff Volume control: right 1) IEC 958 Amendment1, “Digital Audio Interface” Micronas ) dec hex output clock signal at CLKO CLKO is tristate oversampling factor 512/768 oversampling factor 256/384 set output clock according to audio sample rate (see Table 2– ...
Page 38
... MPEG 2.5 (decoding only) reserved MPEG 2 MPEG 1 reserved Layer 3 Layer 2 (decoding only) Layer 1 (decoding only) bitstream protected by CRC bitstream not protected by CRC no CRC error CRC error no invalid frame invalid frame ADVANCE INFORMATION Name All MPEGFrameCount All MPEGStatus1 Micronas ...
Page 39
... Padding Bit bit[8] reserved bit[7:6] Mode bit[5:4] Mode extension (applies to joint stereo only bit[3] Copyright Protect Bit 0/1 bit[2] Copy/Original Bit 0/1 ... Micronas MPEG1, L2 MPEG1, L3 MPEG2, L2/3 free free free ...
Page 40
... The first bit received from the MPEG source is at posi- tion 2 of D0:FD6; the last bit received is at the LSB of D0:fd5. ADVANCE INFORMATION Name MPEGStatus2 Decoder CRCErrorCount Decoder NumberOfAncillary- Bits Decoder AncillaryData Short Read from D0 read 2 words starting at D0:fd5 dd> receive the 2 16-bit words Micronas ...
Page 41
... MSB Ancillary Data Micronas Table 3–9: Settings for the digital volume matrix Memory Name Stereo (default) Mono left Mono right If channels are mixed, care must be taken to prevent clipping at high amplitudes. Therefore the sum of the absolute values of coefficients for one output channel should be less than 1 ...
Page 42
... Reading the codec registers also needs a set-up for the register address and an additional start condition during the actual read cycle. A list of registers is given in Table 3–13 and codec_read (6D ). hex A r1, d1, into the codec register with the number 00 1B r1, d1, ADVANCE INFORMATION : hex Micronas ...
Page 43
... D/A. Then the DC reference volt- age generation for the D/A converter will not be interrupted. INPUT MODE SELECT 00 08 Input Mode Setting bit[15] Mono switch 0 1 bit[14:2] Reserved, must be set to 0 bit[1:0] Deemphasis select Micronas 2 C subaddress 6C hex +19.5 dB +18.0 dB ... +1.5 dB 0.0 dB 1.5 dB 3.0 dB +43.5 dB +42.0 dB ... +22.5 dB +21.0 dB ...
Page 44
... C subaddress 6C hex Linear scaling factor (hex) hex off gain) 100 % (0 dB gain) 200 % (+6 dB gain) stereo through mono matrix applied through right channel is inverted ADVANCE INFORMATION Name DAC_IN_ADC DAC_IN_DSP DAC_OUT_MODE BASS 0 dB Micronas ...
Page 45
... The settings should be: max (bass, treble) + loudness + volume The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz. Micronas 2 C subaddress 6C hex 12 dB ...
Page 46
... MAS 3587F Table 3–12: Codec control registers on I Register Function Address (hex) Micronas Dynamic Bass (MDB MDB Effect Strength bit[15:8] 00 hex 7F hex The MDB effect strength can be adjusted in 1dB steps. A value of 40 yield a medium MDB effect MDB Harmonics bit[15:8] ...
Page 47
... Note: To reset the internal variables, the AVC should be switched off and then on again during any track or source change. For standard applications, the recommended decay time Micronas 2 C subaddress 6C hex 12 dB (maximum volume 113 dB ...
Page 48
... ADVANCE INFORMATION Name QPEAK_L QPEAK_R DQPEAK_L DQPEAK_R Micronas ...
Page 49
... MDB Table 3–14: Suggested MDB settings Function MDB off Low end headphones, medium effect Micronas MDB_FC MDB_SHAPE Fig. 3–4: Micronas Dynamic Bass (MDB): Bass boost in relation to input signal leve MDB_STR MDB_HAR (22 ) (23 ) hex ...
Page 50
... Short Description Analog reference voltage Input for internal microphone amplifier Bias for internal microphone Left A/D input Right A/D input Test enable Crystal oscillator (ext. clock) input Crystal oscillator output Power on reset, active low DSP supply ground Digital output supply ground DSP supply Micronas ...
Page 51
... SYNC 27 VBAT 28 PUP 29 EOD 30 PRTR 31 PRTW PCS 34 PI19 35 PI18 36 PI17 37 PI16 38 PI15 39 PI14 40 PI13 41 PI12 42 SOD Micronas Type Default Connection (if not used) SUPPLY X SUPPLY IN/OUT VDD SUPPLY LV SUPPLY VSS SUPPLY VSS SUPPLY LV IN/OUT VDD IN VSS OUT LV IN/OUT X IN/OUT X OUT LV ...
Page 52
... Reference differential S/PDIF input 1 and 2 Feedback input for left amplifier Analog supply for output amplifiers Left analog output Right analog output Analog ground for output amplifiers Feedback for right output amplifier Analog ground Analog reference ground Internal power supply Analog Supply Micronas ...
Page 53
... Con- nect also to AVSS0/1 and VSS/XVSS. DCSO1/DCSO2 DC/DC converter switch connection. If the respective DC/DC converter is not used, this pin must be left vacant. Micronas VSENS1/VSENS2 Sense input and power output of DC/DC converters. If the respective DC/DC converter is not used, this pin should be connected to a supply. DCEN Enable signal for both DC/DC converters ...
Page 54
... Connection to input terminal of output amplifier.Can be used to connect a capacitance from OUTL respectively OUTR to FILTL respectively FILTR in parallel to feed- back resistor and thus implement a low pass filter to reduce the out-of-band noise of the DAC. ADVANCE INFORMATION OUT OUT OUT loudspeak Micronas ...
Page 55
... PVDD 63 AVDD1 AGNDC MICIN MICBI INL INR TE XTI VSS XTO POR Fig. 4–2: PLQFP64 package (Top view) Micronas OUT IN IN PI15 PI16 PI17 PI18 PI19 PCS PRTW 30 PRTR 29 EOD 28 PUP 27 VBAT 26 SYNC ...
Page 56
... Fig. 4–8: Input/output pins I2CC, I2CD VSENS P DCSO N DCSG Fig. 4–9: Input/output pins DCSO1/2, DCSG1/2, VSENS1/2 XVDD P N XVSS Fig. 4–10: Output pins PRTW, EOD, PRTR, CLKO, SYNC, PUP AVDD P XTI Enable N AVSS Fig. 4–11: Clock oscillator XTI, XTO XTO Micronas ...
Page 57
... AGNDC Fig. 4–14: Analog outputs OUTL(R) and connections for filter capacitors FILTL(R) + 1.25 V VREF Fig. 4–15: Analog ground generation with pin to connect external capacitor Micronas SPDI1, D SPDI2 SPDIR Fig. 4–16: S/PDIF inputs VBAT Fig. 4–17: Battery voltage monitor VBAT AGNDC MAS 3587F ...
Page 58
... Pin Name Min. VDD, XVDD, AVDD0/1, I2CVDD 1) AVDD0/1 VDD, XVDD, I2CVDD I2CC, I2CD 2) OUTL/R 3) DCSO1 DCSO2 ADVANCE INFORMATION Max. Unit 40 85 °C 40 125 °C 650 0.3 V +0.3 V SUP 20 + 0.3 V SUP 0.2 0 +50 mA 1.5 A 1.5 A Micronas ...
Page 59
... XTI at V AVDD Clockamplitude of external clock fed into XTO at V AVDD Clockamplitude of external clock fed into XTO at V AVDD Clockamplitude of external clock fed into XTO at V AVDD Duty cycle Micronas Pin Name Min. 40 VDD, XVDD 2.2 I2CVDD V SUPDn at VDD AVDD0/1 2.2 ...
Page 60
... Input low voltage ILD I Input high voltage IHD 60 ADVANCE INFORMATION Pin Name Min. Typ. XTI, XTO 18.432 Pin Name Min. Typ. I2CC, I2CD 1.4 POR, DCEN 0.9 PI<I>, SI(B)I, V SI(B)C, SUP 0.5 SI(B)D, PR, PCS, TE, DVS Max. Unit MHz 50 ppm 50 ppm Max. Unit Micronas ...
Page 61
... DC/DC-Converter External Circuitry (please refer to application example) C VSENS blocking 1 (<100 m ESR) V Schottky diode threshold voltage TH L Ferrite ring core coil inductance S/PDIF Interface Analog Input C S/PDIF coupling capacitor SPI Micronas Pin Name Min. Typ. AGNDC 1.0 3.3 10 PVDD 3 INL/R 390 MICIN 390 MICBI 3 ...
Page 62
... Test Conditions mA 2.5 V, sampling frequency 32 kHz 2.5 V, sampling frequency 24 kHz 2.5 V, sampling frequency 12 kHz 3.5 V, sampling frequency 32 kHz 2.7 V, sampling frequency 24 kHz µA DSP off, Codec off, DC /DC off, A/D and 2 D/AC off access load load pF µ < V < V pin SUPD Micronas ...
Page 63
... I C input high voltage I2CIH t Wait time W H I2CC L t I2C1 H I2CD as input L H I2CD as output L 2 Fig. 4–18 timing diagram Micronas Pin Name Min. Typ. I2CC 400 I2CC, 300 I2CD I2CC, 300 I2CD I2CC 1250 I2CC 1250 I2CC 80 I2CC 80 ...
Page 64
... MHz, Typ. values for T Crystal Pin Name Min. Typ. SI(B)C 325 SI(B)C, 50 SI(B)D SI(B)D 50 SI(B)C, 50 SI(B)I SI(B)I 50 SI(B)C, 480 SI(B)D min. t SICLK 162 177 325 354 651 708 ADVANCE INFORMATION = Max. Unit Test Conditions kHz Stereo bits per sample (for demand mode see Table 4– Micronas ...
Page 65
... Fig. 4–19: Continuous data stream at serial input this mode, the word strobe SI(B)I is not used and the data are read at the falling edge of the clock (bit 2 in D0:7f1 is set). T SICLK H SI(B SI(B SI(B Fig. 4–20: Serial input signal Micronas T SICLK T T SIDH SIDS T T SIIS SIIH T SIDS MAS 3587F T SIDH ...
Page 66
... Fig. 4–21: Serial output interface timing 18.432 MHz, Typ. values for T Crystal Pin Name Min. Typ. Max. SOC 325 SOC, 0 SOI SOC, 0 SOD T SOCLK T SOISS T SOODC ADVANCE INFORMATION = Unit Test Conditions kHz Stereo S 32 bits per sample ns ns Micronas ...
Page 67
... Fig. 4–23: Sample timing of the SDO interface in 32 bit/sample mode. D0:7f1 settings are: Bit (SOC not inverted), bit (no SOI delay), bit (word strobe inverted), bit (32 bits/sample). Micronas right 16-bit audio sample ...
Page 68
... Micronas ...
Page 69
... H1,L1 t H0,L0 V Signal amplitude Bit value = Bit value = Fig. 4–25: Timing of the S/PDIF output Micronas = 18.432 MHz, Typ. values for T Crystal Pin Name Min. Typ. SPDO 3.072 SPDO 2.822 SPDO 2.048 SPDO 326 SPDO 0 SPDO 0 SPDO 50 SPDO ...
Page 70
... ADVANCE INFORMATION Pin Min. Max. Name PR, EOD 0.010 2000 PR, RTR 40 160 PR, 120 480 PI[19:12] PI[19:12] 160 PI[19:12] 160 RTR 200 30000 PR 480 PR, RTR 160 PR, EOD 40 160 EOD 2.5 500 t t eod eodq high low high low high low high low Micronas Unit ...
Page 71
... MAS 3587F, this time can be expanded up to 4.8 ms once within each frame (see Table 2–2 on page 15) in any case EOD PR RTW PI[19:12] Byte 1 Fig. 4–27: Handshake protocol for reading MPEG data from the PIO-DMA Micronas Table 4–5: PIO output mode timing Symbol ...
Page 72
... SUPA A Codec = off DSP = off DC/ Codec = off DSP = off DC/DC = off V SUPA crystal is used SUPA PP 0 2.2 V SUPA V = 2.7 V SUPA V = 3.3 V SUPA V V Bits 15 SUPA in Reg. 6A hex >2 >2 >3 Bits 15,14 pp SUPA in Reg. 6A hex >2 >2 >3 Micronas ...
Page 73
... Analog Output for AGNDC- Voltage V Analog Output Voltage AC AO2 output gain output gain R Analog line input resistance inAI R Microphone input resistance inMI R Analog output resistance inAO SNR Signal-to-noise ratio of line AI input Micronas Pin Name Min. Typ. Max. OUTL/R 1.56 1.84 2.27 2.20 2.60 3.20 OUTL OUTL/R 1.56 1.84 2.27 2.00 2 ...
Page 74
... OUTL/ (see Fig. 4–31 on page 80) analog gain=0 dB input=-3 dBFS dB 1 kHz sine at 100 mV rms dB 100 kHz sine at 100mV rms referred to VREF V Bits 15 SUPA Reg. 6A hex >2 >2 >3 Micronas ...
Page 75
... ADVANCE INFORMATION Symbol Parameter V Bias voltage for microphone MICBI R Source resistance MICBI I Maximum current microphone MAX bias Micronas Pin Name Min. Typ. Max. MICBI 1.8 2.13 2.62 MICBI 180 MICBI 300 MAS 3587F Unit Test Conditions V Bits 15 SUPA Reg. 6A hex >2 >2 >3 ...
Page 76
... C subaddress 76 ) hex LOAD 0.9...1.5 V, 330 1.8...3.0 V, 330 20...200 mA, LOAD % OUT kHz (see Section 2.9.2. on page 11) kHz VSENSn < 1 µA µA VSENSn converter off LOAD Micronas ...
Page 77
... Load Current (A) Efficiency vs. Load Current DCDC1 (V = 3.0 V) OUT 100 2 1.5 V 1 Load Current (A) Fig. 4–28: Efficiency vs. Load Current Micronas 100 3 1 PFM PWM 100 2 0 PFM PWM 0 1 ...
Page 78
... PFM PWM 0.8 0.6 0.4 0.2 0 0.0 3 LOAD in in ADVANCE INFORMATION Efficiency vs. Load Current DCDC2 (V = 2.2 V) OUT 1 1.5 V 1.2 V 0.9 V PFM PWM Load Current (A) Maximum Load Current vs. Input Voltage DCDC2 V : out 2.2 V 3.0 V 3.5 V PFM PWM 1.0 2.0 Input Voltage (V) Micronas 1 3.0 ...
Page 79
VDC1 Serial memory device e.g. SD-Card MPEG IEC 958 DigiAmp 2 SIBD D 10k SIBC 100n 75 SPDI2 CD/DVD-player IEC 958 SPDI1 100n 75 SPDIR 100n 470p FILTL AVDD0 22 220u OUTL 220u OUTR AVSS0 100 100 ...
Page 80
... Fig. 4–31: External circuitry for the DC/DC converters µH D1, Schottky + C3 = 330 µF VDC1 e.g. 2 330 µF + (low ESR) D Power-On Push Button µH D2, Schottky VDC2 e.g. 2.5 V/3 330 µF + (low ESR) ADVANCE INFORMATION V (Input Voltage) IN (0.9..1.5 V) Star Point Ground Connection very close to Pins DCSG1 and DCSG2 D A Micronas ...
Page 81
... ADVANCE INFORMATION Micronas MAS 3587F 81 ...
Page 82
... By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. ...
Page 83
... This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components. ...