MAS9187 MAS, MAS9187 Datasheet - Page 5

• Manufacturer Part Number: MAS9187
• Description: 12 X 8-bit D to A Converter
• Manufacturer: MAS

OPERATING MODES
DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL)
(note: VREFL=GND in case of MAS9187A1). XRESET pin is used for middle code preset: DAC registers are
reset and middle code will appear at the DAC output.
Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register.
Rising XCS-pin stops data reading and 12 CLK-cycles are used as the input data (4 address bits and 8 data
bits). The last 12 bits before rising XCS are used as input data.
◆ Timing diagram
APPLICATION AND TEST CIRCUIT INFORMATION
SDI
XCS
CLK
V
OUT
Controller
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Data In
Clock
Latch
100 nF
12
13
9
8
XSHDN
CLK
SDI
XCS
MAS9187A2
20
10
VDD
GND
DAC Register Load
+3.0v
VREFL
VREFH
1
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
11
19
18
17
16
15
14
7
6
5
4
3
2
29 January, 2004
DA9187.002
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