IDT72201L25JI8 IDT, Integrated Device Technology Inc, IDT72201L25JI8 Datasheet - Page 9
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IDT72201L25JI8
Manufacturer Part Number
IDT72201L25JI8
Description
IC FIFO 256X9 SYNC 25NS 32-PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet
1.IDT72211L10JG.pdf
(14 pages)
Specifications of IDT72201L25JI8
Function
Synchronous
Memory Size
2.3K (256 x 9)
Data Rate
40MHz
Access Time
25ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
2.25Kb
Access Time (max)
15ns
Word Size
9b
Organization
256x9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
40MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72201L25JI8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72201L25JI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. t
NOTE:
1. When t
©
(If Applicable)
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
Q
REN1,
WCLK
WEN2
and the rising edge of WCLK is less than t
When
The Latency Timings apply only at the Empty Boundary (EF = LOW).
WEN1
RCLK
SKEW1
REN2
0
- Q
Q
D
OE
EF
WCLK
0
WEN2
0
WEN1
REN1,
t
RCLK
REN2
SKEW1
SKEW1
8
is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK
- Q
- D
OE
EF
8
8
≥ minimum specification, t
< minimum specification, t
t
ENS
t
OLZ
FRL
FRL
t
ENH
= t
= 2t
SKEW1
CLK
t
CLK
DS
t
t
+ t
t
ENS
ENS
, then EF may not change state until the next RCLK edge.
+ t
CLKH
SKEW
SKEW
t
t
REF
A
1
t
1 or t
OE
Figure 7. First Data Word Latency Timing
t
SKEW1
CLK
t
CLK
+ t
NO OPERATION
Figure 6. Read Cycle Timing
SKEW
D
0
(First Valid Write)
1
t
OLZ
t
t
FRL
CLKL
t
REF
VALID DATA
(1)
9
t
OHZ
t
ENS
D
t
1
OE
t
SKEW1
(1)
t
A
t
REF
D
2
COMMERCIAL AND INDUSTRIAL
D
0
t
TEMPERATURE RANGES
A
OCTOBER 22, 2008
D
3
2655 drw 08
D
2655 drw 09
1