PDSP1601-MC Mitel Networks Corporation, PDSP1601-MC Datasheet - Page 5

• Manufacturer Part Number: PDSP1601-MC
• Description: ALU and Barrel Shifter
• Manufacturer: Mitel Networks Corporation

Divide by Two
instructions used for right shifting (dividing by two) extended
precision words. These words, (up to 64 bits) may be stored
in the two on-chip register files. When the least significant 16
bit word is shifted, the vacant MSB must be filled with the LSB
from the next most significant 16 bit byte. This is achieved via
the A2RAL, A2RAR or A2RSX instructions which indicate the
source of the new MSB (see SLU INSTRUCTION SET).
MSB must be filled with a duplicate of the original MSB so as
to maintain the correct sign (Sign Extension). This operation
is achieved via the A2SGN instruction (see Table 1).
Constants
OPALT) that force a constant value onto the ALU output.
These values are primarily intended to be used as masks, or
the seeds for mask generation, for example, the OPONE
instruction will set a single bit in the least significant position.
This bit may be rotated any where in the 16 bit field by the
Barrel Shifter, allowing the AND function of the ALU to perform
bit-pick operations on input data.
CLR
the entire device. This instruction has the effect of:
1. Clearing ALU and Barrel Shifter register files to zero.
2. Clearing A and B port input registers to zero.
3. Clearing the R1 and R2 shift control registers to zero.
4. Clearing the internally registered CO bit to zero.
5. Programming the BFP flag to detect overflow conditions.
KEY
SV
R1
R2
PE
I
O
X
The ALU has four (A2SGN, A2RAL, A2RAR, A2RSX)
When the most significant 16 bit byte is right shifted, the
The ALU has four instructions (OPONE, OPBYT, OPNIB,
The ALU instruction CLRXX is used as a Master Reset for
= Shift Value
= Register 1
= Register 2
= Priority Encoder Output
=> SV Port operates as an Input
=> SV Port operates as an Output
=> SV Port in a High Impedance State
Inst
C
D
A
B
E
F
0
1
2
3
4
5
6
7
8
9
IS3-IS0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mnemonic
Table 2 Barrel shifter instructions
NRMXX
NRMR1
NRMR2
BSRSV
ASRSV
LSRSV
ASRR1
ASRR1
BSLSV
LSRR1
LSRR2
LR1SV
LR2SV
LSLSV
LSLR1
LSLR2
MNEMONICS
LSXYY
BSXYY Barrel Shift,
ASXYY Arithmetic Shift, X
LXXYY
NRMYY Normalise by PE, Output PE value on SV Port, Load YY Reg
Logical Shift Right by SV
Logical Shift Left by SV
Barrel Shift Right by SV
Barrel Shift Left by SV
Logical Shift Right by R1
Logical Shift Left by R1
Logical Shift Right by R2
Logical Shift Left by R2
Load Register 1 From SV
Load Register 2 From SV
Arithmetic Shift Right by SV
Arithmetic Shift Right by R1
Arithmetic Shift Right by R2
Normalise Output PE
Normalise Output PE, Load R1
Normalise Output PE, Load R2
The Barrel Shifter
Table 2. The input to the Barrel Shifter is selected by the S
MUX. Data will fall through from the selected register, through
the S MUX and the Barrel Shifter to the shifter output register
file in 100ns.
instructions will not start executing until the rising edge of CLK
latches the instruction into the device.
Shifts in either direction.
A.
B.
C.
Shifter input as illustrated in Table 3. The type of shift and the
amount are determined by the shift control block. The shift
control block (see Fig.3) accepts and decodes the four bit ISO-
3 instruction.
encoder and two, user programmable 4 bit registers R1 and
R2.
passed onto the Barrel Shifter, there are:
1. The Priority Encoder
2. The SV input
3. The R1 register
4. The R2 register
Logical Shift,
Load
The Barrel Shifter supports 16 instructions as detailed in
The Barrel Shifter instructions are latched, such that the
The Barrel Shifter is capable of Logical Arithmetic or Barrel
The amount of shift applied is encoded onto the 4 bit Barrel
There are four possible sources of shift value that can be
Operation
Logical shifts discard bits that exit the 16 bit field and fill
spaces with zeros.
Arithmetic shifts discard bits that exit the 16 bit field and
fill spaces with duplicates of the original MSB.
Barrel Shifts rotate the 16 bit fields such that bits tha exit
the 16 bit field to the left or right reappear in the vacant
spaces on the right or left.
The shift control block contains a priority
X
X
XX = Target
= Direction YY = Source of Shift Value
= Direction YY = Source of Shift Value
= Direction YY = Source of Shift Value
I/O
I
I
I
I
X
X
X
X
I
I
I
X
X
O
O
O
YY = Source
PDSP1601 MC
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