PDSP16116AB0GG Mitel Networks Corporation, PDSP16116AB0GG Datasheet - Page 6

• Manufacturer Part Number: PDSP16116AB0GG
• Description: 16 X 16 Bit Complex Multiplier
• Manufacturer: Mitel Networks Corporation

PDSP16116
Result Correction
sentation it is possible to represent 21 exactly but not 11. With
conventional multipliers this causes a problem when 21 is mul-
tiplied by 21 as the multiplier produces an incorrect result. The
PDSP16116 includes a trap to ensure that the most positive
number (value = 1·2
the incorrect result. The multiplier result is therefore always a
correct fractional value. Fig.2 shows the value ‘1’ being multi-
plexed into the data path controlled by four comparators.
6
NORMAL MODE OPERATION
mode of operation is selected. This mode supports all complex
multiply operations that do not require block floating point
arithmetic.
X and Y input registers via the X and Y Ports on the rising edge
Adder/Subtractor Stage
are passed to two 32-bit adder/subtractors. The adder calcu-
lates the imaginary result [(XR 3 YI) 1 (XI 3 YR)] and the
Rounding
significant 16 bits of the full 32-bit result from the shifter. If the
ROUND signal is active (high), then bit 16 is set to ‘1’, rounding
the most significant 16 bits of the shifted result. (The least
Multiplier Stage
to the four multipliers to start a new complex multiply operation.
Each complex multiply operation requires four partial products
(XR3YR), (XR3YI), (XI3YR), (XI3YI), all of which are calculated
in parallel by the four 16316 multipliers. Only one clock cycle is
Due to the nature of the fraction two’s complement repre-
When the MBFP mode select input is held low the ‘Normal’
Complex two’s complement fractional data is loaded into the
The 31-bit real and imaginary results from the multipliers
The ROUND control when asserted rounds the most
On each clock cycle the contents of the input registers are passed
The effective weighting of the sign bit is 22
The effective weighting of the sign bit is 22
The effective weighting of the sign bit is 22
Where S = sign bit, which has an effective weighting of 22
The value of the 16-bit two’s complement word is (213S)1(bit1432
Bit Number
Weighting
Bit Number
Weighting
Bit Number
Weighting
Bit Number
Weighting
230
, hex = 7FFFFFFFF) is substituted for
31
31
15
30
S
S
S
S
30
30
2
2
2
14 13 12 11 10
29 28 27 26 25 24
2
0
–
–
0
1
1
2
29 28 27 26
2
29 28 27
2
2
–
–
–
–
1
1
2
2
ROUNDED VALUE
2
2
2
2
–
–
–
–
2
2
3
3
2
2
2
2
–
–
–
–
3
3
4
4
2
2
2
–
0
1
1
–
–
4
5
5
2
18
2
2
9
–
–
–
1 2
6
6
of CLK. The X and Y port registers are individually enabled by
the
quired to be permanently enabled, then these signals may be
tied to ground.
are each assumed to have the following format:
subtractor calculates the real result (XR 3 YR) = (XI 3 YI).
Each adder/subtractor produces a 32-bit result with the
following format:
significant 16 bits are unaffected). Inserting a ‘1’ ensures that
the rounding error is never greater than 1 LSB and that no DC
bias is introduced as a result of the rounding processes. The
format of the rounded result is:
Complex Conjugation
asserting the CONX or CONY signals respectively. Asserting
either of these signals has the effect of inverting (multiplying
by 21 ) the imaginary component of the respective input. Table 3
shows the effect of CONX and CONY on the X and Y inputs.
required to complete the multiply stage before the multiplier results
are loaded into the multiplier output registers for passing on to the
adder/ subtractors in the next cycle. Each multiplier produces a 31-
bit result with the duplicate sign bit eliminated. The format of the
output data from the multipliers is:
2
2
2
17 16 15 14 13
8
–
8
–
CONX
–
22
The Real and Imaginary components of the fractional data
13
Either the X or Y input data may be complex conjugated by
Low
High
Low
High
7
CEX
2
2
2
2
7
–
7
7
–
–
–
23
14
23
0
8
and
2
2
2
2
6
–
6
6
–
–
–
24
15
24
CONY
9
CEY
Low
Low
High
High
2
2
2
2
5
–
5
5
–
–
–
Table 3 Conjugate functions
25
16
10
25
21
signals respectively. If the registers are re-
2
2
2
2
)1(bit1332
4
–
4
4
–
–
–
26
17
11
26
X 3 Y
Conj. X 3 Y
X 3 Conj. Y
Invalid
LSBs
2
Function
2
2
3
–
3
3
–
–
27
12
27
2
2
2
2
2
–
2
–
2
2
–
–
22
28
28
13
28
)1(bit1232
2
2
2
2
1
–
1
1
–
1
–
–
29
29
14
29
(XR 1 XI)3(YR 1 YI)
(XR 2 XI)3(YR 1 YI)
(XR 1 XI)3(YR 2 YI)
Invalid
2
2
2
2
0
–
0
0
0
–
–
–
30
30
15
30
Operation
23
) …