PDSP16256A Zarlink Semiconductor, PDSP16256A Datasheet - Page 10

• Manufacturer Part Number: PDSP16256A
• Description: Programmable FIR Filter
• Manufacturer: Zarlink Semiconductor

PDSP16256/A
Filter Accuary
Input data and coefficients are both represented by 16-
bit two’s complement numbers. The coefficients are
converted to twelve bits by rounding towards zero. This
INPUT DATA
is achieved as follows. If the coefficient is positive then
the least significant 4 bits are discarded. If the coefficient
is negative then the logical ‘OR’ of the least significant 4
COEFFICIENT
bits are added to the remainder of the word. Twelve bit
coefficients can be used directly provided the least
significant four bits are set to zero.
ADDER
The FIR filter results are calculated using a multiplier
accumulator structure as shown in Fig. 10. The trunca-
tion and word growth allowed for in the data path are
explained in Fig. 10. The 16-bit data and 12-bit coeffi-
cient inputs (each with one sign bit before the binary
point), are presented to the multiplier. This produces a
ACCUMULATOR
RESULT
28-bit result with two bits before the binary point. Produc-
ing the full 28-bit result ensures that if both the data and
coefficients are set to logic 1 a valid result is generated.
Prior to entering the accumulator the least significant 4
Figure. 10 Multiplier Accumulator
bits of the multiplier result are truncated and the resulting
24 bits sign extended to 32 bits. The final accumulator
result is 32 bits with 10 bits before the binary point. Thus
9 bits of word growth are allowed within the accumulator.
All accumulator bits are made available on the output
pins.
In cascade mode the middle 16 bits from the network A
accumulator are fed round to the network B data inputs,
see Fig. 11.
Figure. 11 Filter accuracy
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