83C748 Philips Semiconductors, 83C748 Datasheet - Page 12

• Manufacturer Part Number: 83C748
• Description: 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ low pin count
• Manufacturer: Philips Semiconductors

1. Address should be valid at least 24t
2. For a pure verify mode, i.e., no program mode in between, t
Philips Semiconductors
Security Bits
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
1. Additional programming of the USER EPROM is inhibited.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
EPROM PROGRAMMING AND VERIFICATION
T
NOTES:
1999 Apr 15
amb
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYMBOL
still be performed.
AVGL
GHAX
DVGL
GHDX
SHGL
GHSL
GLGH
AVQV
GHGL
MASEL
HAHLD
HASET
ADSTA
= 21 C to +27 C, V
CLCL
1
2
Oscillator/clock frequency
Address setup to P0.1 (PROG–) low
Address hold after P0.1 (PROG–) high
Data setup to P0.1 (PROG–) low
Data hold after P0.1 (PROG–) high
V
V
P0.1 (PROG–) width
V
P0.1 (PROG–) high to P0.1 (PROG–) low
ASEL high time
Address hold time
Address setup to ASEL
Low address to valid data
PP
PP
PP
setup to P0.1 (PROG–) low
hold after P0.1 (PROG–)
low (V
CC
= 5V 10%, V
CC
) to data valid
CLCL
PARAMETER
SS
before the rising edge of P0.2 (V
= 0V
AVQV
is 14t
12
CLCL
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C748 on ports 1 and 3.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
PP
maximum.
).
10 s + 24t
48t
38t
36t
13t
13t
2t
MIN
1.2
CLCL
10
10
90
10
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
48t
48t
83C748/87C748
MAX
110
CLCL
CLCL
6
Preliminary specification
UNIT
MHz
s
s
s
s