83C749 Philips Semiconductors, 83C749 Datasheet - Page 16

• Manufacturer Part Number: 83C749
• Description: 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ 5 channel 8-bit A/D/ PWM/ low pin count
• Manufacturer: Philips Semiconductors

*
1. Address should be valid at least 24t
2. For a pure verify mode, i.e., no program mode in between, t
Philips Semiconductors
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C749 on ports 1 and 3.
Table 3. Implementing Program/Verify Modes
NOTE:
EPROM PROGRAMMING AND VERIFICATION
T
NOTES:
1998 Apr 23
Program user EPROM
Verify user EPROM
Program key EPROM
Verify key EPROM
Program security bit 1
Program security bit 2
Verify security bits
amb
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVGL
GHAX
DVGL
DVGL
GHDX
SHGL
GHSL
GLGH
AVQV
GHGL
SYNL
SYNH
MASEL
MAHLD
HASET
ADSTA
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
SYMBOL
Pulsed from V
CLCL
= 21 C to +27 C, V
1
2
Oscillator/clock frequency
Address setup to P0.1 (PROG–) low
Address hold after P0.1 (PROG–) high
Data setup to P0.1 (PROG–) low
Data setup to P0.1 (PROG–) low
Data hold after P0.1 (PROG–) high
V
V
P0.1 (PROG–) width
V
P0.1 (PROG–) high to P0.1 (PROG–) low
P0.0 (sync pulse) low
P0.0 (sync pulse) high
ASEL high time
Address hold time
Address setup to ASEL
Low address to address stable
IH
PP
PP
PP
to V
setup to P0.1 (PROG–) low
hold after P0.1 (PROG–)
low (V
OPERATION
IL
CC
and returned to V
= 5V 10%, V
CC
) to data valid
CLCL
PARAMETER
SS
IH
before the rising edge of P0.2 (V
= 0V
.
AVQV
SERIAL CODE
is 14t
16
296H
296H
292H
292H
29AH
298H
29AH
CLCL
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
PP
maximum.
).
10 s + 24t
48t
38t
38t
36t
13t
13t
13t
4t
8t
2t
MIN
1.2
CLCL
CLCL
CLCL
10
10
90
10
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
P0.1 (PGM/)
V
V
V
–*
–*
–*
–*
IH
IH
IH
48t
83C749/87C749
MAX
110
CLCL
6
Preliminary specification
P0.2 (V
V
V
V
V
V
V
V
PP
PP
PP
PP
IH
IH
IH
PP
UNIT
MHz
)
s
s
s
s