87C196 Intel Corporation, 87C196 Datasheet - Page 31

• Manufacturer Part Number: 87C196
• Description: CHMOS 16-BIT MICROCONTROLLER
• Manufacturer: Intel Corporation

87C196CA DESIGN CONSIDERATIONS
The 87C196CA device is a memory scalar of the
87C196KR device with integrated CAN 2 0 The CA
is designed for strict functional and electrical com-
patibility to the Kx family as well as integration of on-
chip networking capability The 87C196CA has few-
er peripheral functions than the 196KR due in part
to the integration of the CAN peripheral Following
are the functionality differences between the 196KR
and 196CA devices
196KR Features Unsupported on the 196CA
(1) External Memory Removal of the Buswidth pin
(2) Auto-Programming Mode The 87C196CA de-
(3) EPA4 through EPA7 Since the CA device is
(4) Slave Port Support The Slave port can not be
(5) Port Functions Some port pins have been re-
Analog Channels 0 and 1
INST Pin Functionality
SLPINT and SLPCS Pin Support
HLD HLDA Functionality
External Clocking Direction of Timer 1
Quadrature Clocking Timer 1
Dynamic Buswidth
EPA Capture Channels 4 –7
means the bus cannot dynamically switch from
8- to 16-bit bus mode or vice versa The pro-
grammer must define the bus mode by setting
the associated bits in the CCB
vice will ONLY support the 16-bit zero wait state
bus during auto-programming
based on the KR design these functions are in
the device however there are no associated
pins A programmer can use these as compare-
only channels or for other functions like software
timer start an A D conversion or reset timers
used on the 196CA due to a function change for
P5 4 SLPINT and P5 1 SLPCS not being bond-
ed-out
moved P5 1 P6 2 P6 3 P1 4 through P1 7
P2 3 P2 5 P0 0 and P0 1 The PxREG PxSSEL
and PxIO registers can still be updated and read
The programmer should not use the correspond-
ing bits associated with the removed port pins to
conditionally branch in software Treat these bits
as RESERVED
(6) EPA Timer RESET Write Conflict If the user
(7) Valid Time Matches The timer must incre-
(8) Write Cycle during Reset If RESET occurs dur-
(9) Indirect Shift Instruction The upper 3 bits of
(10) P2 7 (CLKOUT) P2 7 (CLKOUT) does not op-
ing a write cycle the contents of the external
memory device may be corrupted
the byte register holding the shift count are not
masked completely If the shift count register has
the value 32
operand will be shifted 32 times This should
have resulted in no shift taking place
Additionally these port pins should be setup in-
ternally by software as follows
1 Written to PxREG as ‘‘1’’ or ‘‘0’’
2 Configured as Push Pull PxIO as ‘‘0’’
3 Configured as LSIO
writes to the EPA timer at the same time that the
timer is reset it is indeterminate which will take
precedence Users should not write to a timer if
using EPA signals to reset it
ment decrement to the compare value for a
match to occur A match does not occur if the
timer is loaded with a value equal to an EPA
compare value Matches also do not occur if a
timer is reset and 0 is the EPA compare value
erate in open drain mode
Open Drain output ‘’1’’ or as an Input pin
This device is CMOS
This configuration will effectively strap the pin
either high or low DO NOT Configure as
c
n where n
87C196CA 87C196CB
e
1 3 5 or 7 the
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