87C54-20 Intel Corporation, 87C54-20 Datasheet - Page 15

• Manufacturer Part Number: 87C54-20
• Description: CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM
• Manufacturer: Intel Corporation

Normally EA V
fore ALE PROG is to be pulsed Then EA V
raised to V
EA V
age on the EA V
high level before a verify is attempted Waveforms
and detailed timing specifications are shown in later
sections of this data sheet
Quick Pulse Programming Algorithm
The 87C54 can be programmed using the Quick
Pulse Programming Algorithm for microcontrollers
The features of the new programming method are a
lower V
er programming pulse It is possible to program the
entire 16K bytes of EPROM memory in less than 50
seconds with this algorithm
To program the part using the new algorithm V
must be 12 75V
for 100
the byte just programmed may be verified After pro-
gramming the entire array should be verified The
Program Lock features are programmed using the
same method but with the setup as shown in Table
3 The only difference in programming Program Lock
features is that the Program Lock features cannot be
directly verified Instead verification of programming
is by observing that their features are enabled
See Table 3 for proper input on these pins
PP
PP
is returned to a valid high voltage The volt-
s 25 times as shown in Figure 12 Then
(12 75V as compared to 21V) and a short-
PP
PP
ALE PROG is pulsed low and then
PP
g
is held at logic high until just be-
0 25V ALE PROG is pulsed low
pin must be at the valid EA V
Figure 11 Programming the EPROM
PP
PP
PP
is
Note that the EA V
above the maximum specified V
amount of time Even a narrow glitch above that volt-
age level can cause permanent damage to the de-
vice The V
free of glitches
Program Verification
If the Program Lock Bits have not been pro-
grammed the on-chip Program Memory can be read
out for verification purposes if desired either during
or after the programming operation The address of
the Program Memory location to be read is applied
to Port 1 and pins P2 0 – P2 5 The other pins should
be held at the ‘‘Verify’’ levels indicated in Table 3
The contents of the addressed locations will come
out on Port 0 External pullups are required on Port 0
for this operation
If the Encryption Array in the EPROM has been pro-
grammed the data present at Port 0 will be Code
Data XNOR Encryption Data The user must know
the Encryption Array contents to manually ‘‘unen-
crypt’’ the data during verify
The setup which is shown in Figure 13 is the same
as for programming the EPROM except that pin P2 7
is held at a logic low or may be used as an active
low read strobe
PP
AUTOMOTIVE 87C54 87C54-20
source should be well regulated and
PP
pin must not be allowed to go
270849 –19
PP
level for any
15