87C575 Philips Semiconductors, 87C575 Datasheet - Page 20

• Manufacturer Part Number: 87C575
• Description: 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless/ 4 comparator/ failure detect circuitry/ watchdog timer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
1998 May 01
NOTE:
*SMOD0 is located at PCON6.
**f
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
OSC
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
Tl
Rl
= oscillator frequency
OSC/12
PRE2
PRE1
PRE0
Bit Addressable
Bit:
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
0
0
1
1
SCON Address = 98H
DECODE
(SMOD0 = 0/1)*
SM0/FE
7
SM1
0
1
0
1
64
000
001
010
011
100
101
110
111
SM1
Mode
6
64
0
1
2
3
Figure 18. SCON: Serial Port Control Register
128
SM2
5
Description
shift register
8-bit UART
9-bit UART
9-bit UART
2
Figure 17. Watchdog Prescaler
256
REN
4
2
512
Baud Rate**
f
variable
f
variable
OSC
OSC
20
TB8
2
/12
/64 or f
3
1024
OSC
2
RB8
/32
2
2048
2
4096
Tl
1
2
8192
Rl
0
2
80C575/83C575/
Reset Value = 0000 0000B
DOWN COUNTER
TO WATCHDOG
Product specification
87C575
SU00243
SU00043