DSP56F803 Motorola Inc, DSP56F803 Datasheet

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... CGDB XAB1 XAB2 INTERRUPT IPBB CONTROLS CONTROLS 16 16 COP RESET MODULE CONTROLS IPBus Bridge ADDRESS BUS [8:0] (IPBB) DATA BUS [15:0] Go to: www.freescale.com DSP56F803/D Rev. 13.0, 02/2004 56F803 16-bit words each of external TM port for debugging DDA SSA 6* Analog Reg Low Voltage Supervisor ...

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Freescale Semiconductor, Inc. Part 1 Overview 1.1 56F803 Features 1.1.1 Digital Signal Processing Core • Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency ...

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Freescale Semiconductor, Inc. • Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external pins and Timer D with two pins • CAN 2.0 B module with 2-pin ports for transmit and receive ...

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Freescale Semiconductor, Inc. Program and Data Flash memories can be independently bulk The Boot Flash memory can also be either bulk- or page A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM) module. ...

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... Description Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications to: www.freescale.com Product Documentation Order Number DSP56800FM/D DSP56F801-7UM/D DSP56F803/D DSP56F803PB/D DSP56F803E/D 1 Voltage ...

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Freescale Semiconductor, Inc. Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F803 are organized into functional groups, as shown in as illustrated in Figure 2. In Table 3 present on a pin. Table 2. Functional ...

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Freescale Semiconductor, Inc Power Port V SS Ground Port V DDA Power Port V SSA Ground Port VCAPC Other Supply Ports EXTAL PLL and XTAL Clock CLKO A0-A5 External A6-7 (GPIOE2-E3) Address Bus or GPIO A8-15 (GPIOA0-A7) External ...

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Freescale Semiconductor, Inc. 2.2 Power and Ground Signals No. of Pins Signal Name 6 V Power—These pins provide power to the internal structures of the chip, and DD should all be attached Analog Power—This pin is ...

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Freescale Semiconductor, Inc. Table 6. PLL and Clock (Continued) No. of Signal Signal State During Pins Name Type 1 CLKO Output Chip-driven 2.4 Address, Data, and Bus Control Signals Table 7. Address Bus Signals No. of Signal Signal State During ...

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Freescale Semiconductor, Inc. Table 9. Bus Control Signals No. of Signal Signal State During Pins Name Type Reset 1 PS Output Tri-stated 1 DS Output Tri-stated 1 WR Output Tri-stated 1 RD Output Tri-stated 2.5 Interrupt and Program Control Signals ...

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Freescale Semiconductor, Inc. Table 10. Interrupt and Program Control Signals (Continued) No. of Signal Signal Pins Name Type 1 RESET Input (Schmitt) 1 EXTBOOT Input (Schmitt) 2.6 Pulse Width Modulator (PWM) Signals Table 11. Pulse Width Modulator (PWMA) Signals No. ...

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Freescale Semiconductor, Inc. 2.7 Serial Peripheral Interface (SPI) Signals Table 12. Serial Peripheral Interface (SPI) Signals No. of Signal Signal Pins Name Type 1 MISO Input/ Output GPIOE6 Input/ Output 1 MOSI Input/ Output GPIOE5 Input/ Output 1 SCLK Input/ ...

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Freescale Semiconductor, Inc. 2.8 Quadrature Decoder Signals Serial Communications Table 13. Quadrature Decoder (Quad Dec0) Signals No. of Signal Signal Pins Name Type 1 PHASEA0 Input TA0 Input/Output 1 PHASEB0 Input TA1 Input/Output 1 INDEX0 Input TA2 Input/Output 1 HOME0 ...

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Freescale Semiconductor, Inc. 2.11 Analog-to-Digital Converter (ADC) Signals Table 16. Analog to Digital Converter Signals No. of Signal Signal State During Pins Name Type 4 – Input ANA0 3 – 4 Input ANA4 7 1 VREF Input 2.12 Quad Timer ...

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Freescale Semiconductor, Inc. Part 3 Specifications 3.1 General Characteristics The 56F803 is fabricated in high-density CMOS with 5-V tolerant TTL-compatible digital inputs. The term “5-V tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, ...

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Freescale Semiconductor, Inc. Table 20. Recomended Operating Conditions Characteristic Supply voltage, digital Supply Voltage, analog ADC reference voltage Ambient operating temperature Table 21. Thermal Characteristics Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Four layer ...

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Freescale Semiconductor, Inc. 5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. See Section 5.1 from ...

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Freescale Semiconductor, Inc. Table 22. DC Electrical Characteristics (Continued) Operating Conditions SSA Characteristic Input capacitance Output capacitance V supply current DD 6 Run 7 Wait Stop Low Voltage Interrupt, external power supply ...

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Freescale Semiconductor, Inc. 180 IDD Digital 150 120 Figure 3. Maximum Run IDD vs. Frequency (see Note 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 are tested using the V table. In Figure 4 ...

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Freescale Semiconductor, Inc. Data1 Valid Data1 Data Invalid State Data Active 3.4 Flash Memory Characteristics Table 23. Flash Memory Truth Table 1 Mode XE YE Standby L L Read H H Word Program H H Page Erase H L Mass ...

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Freescale Semiconductor, Inc. Table 25. Flash Timing Parameters Operating Conditions SSA Characteristic Symbol Program time T Erase time T Mass erase time Endurance 1 D Data Retention @ 5000 ...

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Freescale Semiconductor, Inc. IFREN XADR XE YADR YE DIN PROG Tnvs NVSTR Tpgs Figure 6. Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR 22 For More Information On This Product, Tadh Tads Tprog Thv Terase Figure 7. Flash ...

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Freescale Semiconductor, Inc. IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Figure 8. Flash Mass Erase Cycle 3.5 External Clock Operation The 56F803 system clock can be derived from an external crystal or an external system clock signal. To generate ...

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Freescale Semiconductor, Inc. This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit. EXTAL XTAL Figure 9. Connecting to a Crystal Oscillator 3.5.2 Ceramic ...

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Freescale Semiconductor, Inc. Table 26. External Clock Operation Timing Requirements Operating Conditions SSA Characteristic Frequency of operation (external clock driver Clock Pulse Width , 1. See Figure 11 for details ...

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Freescale Semiconductor, Inc. 3.6 External Bus Asynchronous Timing Table 28. External Bus Asynchronous Timing Operating Conditions SSA Characteristic Address Valid to WR Asserted WR Width Asserted Wait states = 0 Wait states ...

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Freescale Semiconductor, Inc. A0–A15, PS, DS (See Note AWR t WRWR WR t WRD t DOS D0–D15 Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 13. External Bus Asynchronous Timing 3.7 ...

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Freescale Semiconductor, Inc. Table 29. Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued) Operating Conditions SSA Characteristic Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) OMR Bit 6 ...

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Freescale Semiconductor, Inc. A0–A15, PS, DS, RD IDM IRQA, IRQB General Purpose I/O Pin t IG IRQA, IRQB Figure 16. External Level-Sensitive Interrupt Timing IRQA, IRQB A0–A15, PS, DS, RD, WR Figure 17. Interrupt from Wait State Timing ...

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Freescale Semiconductor, Inc. IRQA A0–A15 PS, DS, RD, WR Figure 19. Recovery from Stop State Using IRQA Interrupt Service 3.8 Serial Peripheral Interface (SPI) Timing Operating Conditions SSA Characteristic Cycle time Master ...

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Freescale Semiconductor, Inc. Operating Conditions SSA Characteristic Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave ...

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Freescale Semiconductor, Inc. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 21. SPI Master Timing (CPHA = 1) SS (Input) SCLK (CPOL = 0) (Input) t ELD SCLK ...

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Freescale Semiconductor, Inc. SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output MOSI (Input) Figure 23. SPI Slave Timing (CPHA = 1) 3.9 Quad Timer Timing Operating Conditions: V ...

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Freescale Semiconductor, Inc. Timer Inputs P IN Timer Outputs P OUT 3.10 Quadrature Decoder Timing Table 32. Quadrature Decoder Timing Operating Conditions SSA Characteristic Quadrature input period Quadrature input high/low period Quadrature ...

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Freescale Semiconductor, Inc. 3.11 Serial Communication Interface (SCI) Timing Operating Conditions SSA Characteristic 1 Baud Rate 2 RXD Pulse Width 3 TXD Pulse Width the frequency of operation of ...

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Freescale Semiconductor, Inc. Table 34. ADC Characteristics (Continued) Operating Conditions SSA performance), ADC clock = 4MHz, 3.0–3.6V, T Characteristic Power-up time Conversion time Sample time Input capacitance 5 Gain Error (transfer gain) ...

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Freescale Semiconductor, Inc. 3.13 Controller Area Network (CAN) Timing Operating Conditions SSA Characteristic Baud Rate 1 Bus Wakeup detection 1. If Wakeup glitch filter is enabled during the design initialization and also ...

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Freescale Semiconductor, Inc. 3.14 JTAG Timing Operating Conditions SSA Characteristic 2 TCK frequency of operation TCK cycle time TCK clock pulse width TMS, TDI data set-up time TMS, TDI data hold time ...

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Freescale Semiconductor, Inc. TCK (Input) TDI TMS (Input TDO (Output TDO (Output ) t DV TDO (Output) Figure 31. Test Access Port Timing Diagram TRST (Input) t TRST Figure 32. TRST Timing Diagram ...

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Freescale Semiconductor, Inc. Part 4 Packaging 4.1 Package and Pin-Out Information 56F803 This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F803. D10 D11 D12 PIN 1 D13 D14 D15 ...

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Freescale Semiconductor, Inc. Table 37. 56F803 Pin Identification By Pin Number Pin No. Signal Name Pin No. 1 D10 26 2 D11 27 3 D12 28 4 D13 29 5 D14 30 6 D15 ...

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Freescale Semiconductor, Inc. S 0.15 (0.006) AC T-U S -T- - 0.15 (0.006 T-U AE -AB- 96X (24X PER SIDE 0.25 (0.010 GAUGE PLANE DETAIL AD ...

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Freescale Semiconductor, Inc. Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, T Equation Where ambient temperature ° package junction-to-ambient thermal resistance ...

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Freescale Semiconductor, Inc. • Use the value obtained by the equation (T case determined by a thermocouple. The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package ...

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Freescale Semiconductor, Inc. 5.2 Electrical Design Considerations This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages ...

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... Table 38. 56F803 Ordering Information Supply Part Voltage 56F803 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 46 For More Information On This Product, Pin Package Type Count 100 Go to: www.freescale.com Frequency Order Number (MHz) 80 DSP56F803BU80 56F803 Technical Data ...

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Freescale Semiconductor, Inc. 56F803 Technical Data For More Information On This Product, Go to: www.freescale.com Electrical Design Considerations 47 ...

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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2004 DSP56F803/D Go to: www.freescale.com ...