DSP56F807 Motorola Inc, DSP56F807 Datasheet - Page 11

• Manufacturer Part Number: DSP56F807
• Description: 56F807 16-bit Hybrid Processor
• Manufacturer: Motorola Inc

2.6 GPIO Signals
2.7 Pulse Width Modulator (PWM) Signals
56F807 Technical Data
No. of
No. of
No. of
Pins
Pins
Pins
1
1
8
6
6
3
4
6
EXTBOOT
FAULTA0-3
GPIOB0-G
GPIOD0-G
PWMA0-5
PWMB0-5
Table 11. Dedicated General Purpose Input/Output (GPIO) Signals
RESET
Signal
Name
Signal
PIOB7
PIOD5
ISA0-2
Name
Signal
Name
Table 12. Pulse Width Modulator (PWMA and PWMB) Signals
Table 10. Interrupt and Program Control Signals (Continued)
(Schmitt)
(Schmitt)
Signal
(Schmitt)
(Schmitt)
Signal
Output
Output
Type
Input
Input
Type
Input
Input
Signal
Output
Output
Type
Input
Input
or
or
Freescale Semiconductor, Inc.
For More Information On This Product,
State During
State During
State During
Tri- stated
Tri- stated
Reset
Reset
Input
Input
Input
Input
Reset
Input
Input
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Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and
placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial
chip operating mode is latched from the EXTBOOT pin. The
internal reset signal will be deasserted synchronous with the
internal clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should
be asserted together. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
External Boot—This input is tied to V
from off-chip memory. Otherwise, it is tied to VSS.
Port B GPIO—These eight pins are dedicated General
Purpose I/O (GPIO) pins that can individually be programmed
as input or output pins.
After reset, the default state is GPIO input.
Port D GPIO—These six pins are dedicated GPIO pins that
can individually be programmed as an input or output pins.
After reset, the default state is GPIO input.
PWMA0-5— Six PWMA output pins.
ISA0-2— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
FAULTA0-3— These Fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions
originate off-chip.
PWMB0-5— Six PWMB output pins.
Signal Description
Signal Description
Signal Description
DD
to force device to boot
GPIO Signals
11