89C51 Philips Semiconductors, 89C51 Datasheet
89C51
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89C51 Summary of contents
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... Flash Product specification Replaces Datasheets 89C51 of 1999 Apr 01 and 89C52/89C54/89C58 of 1999 Apr 01 hilips Semiconductors INTEGRATED CIRCUITS 1999 Oct 27 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash DESCRIPTION The 89C51/89C52/89C54/89C58 contain a non-volatile FLASH program memory that is parallel programmable. For devices that are serial programmable (In System Programmable (ISP) with a boot loader), see the 89C51RC+/89C51RD+ datasheet. Both families are Single-Chip 8-bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family ...
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... V SS RAM ADDR RAM REGISTER B ACC REGISTER PSEN ALE TIMING AND EAV PP CONTROL RST PD OSCILLATOR XTAL1 XTAL2 1999 Oct 27 89C51/89C52/89C54/89C58 P0.0–P0.7 P2.0–P2.7 PORT 0 PORT 2 DRIVERS DRIVERS PORT 0 PORT 2 LATCH LATCH STACK POINTER TMP2 TMP1 ALU SFRs TIMERS PSW PORT 1 PORT 3 LATCH ...
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... P2.6/A14 T0/P3 P2.5/A13 T1/P3.5 15 WR/P3 P2.4/A12 RD/P3 P2.3/A11 XTAL2 18 23 P2.2/A10 22 P2.1/A9 XTAL1 P2.0/A8 SS SU01063 1999 Oct 27 89C51/89C52/89C54/89C58 Ceramic and Plastic Leaded Chip Carrier Pin Functions ADDRESS AND DATA BUS T2 T2EX Pin Function 1 NIC* 2 P1.0/T2 3 P1.1/T2EX 4 P1.2 ADDRESS BUS 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7 SU00830 10 RST 11 P3 ...
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... DC Electrical Characteristics Port 3 also serves the special features of the IL 89C51/89C52/89C54/89C58, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash Table 1. 89C51/89C52/89C54/89C58 Special Function Registers DIRECT SYMBOL DESCRIPTION ADDRESS ACC* Accumulator E0H AUXR# Auxiliary 8EH AUXR1# Auxiliary 1 A2H B* B register F0H DPTR: Data Pointer (2 bytes) DPH Data Pointer High 83H DPL Data Pointer Low ...
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... Flash FLASH EPROM MEMORY General Description The 89C51/89C52/89C54/89C58 FLASH reliably stores memory contents even after 100 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling ...
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... Power-down Internal Power-down External 1999 Oct 27 89C51/89C52/89C54/89C58 Design Consideration When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited ...
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... EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Figure 1. Timer/Counter 2 (T2CON) Control Register 1999 Oct 27 89C51/89C52/89C54/89C58 Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. ...
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... User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 3. Timer 2 Mode (T2MOD) Control Register 1999 Oct 27 89C51/89C52/89C54/89C58 TR2 1 16-bit Auto-reload 1 ...
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... C/ C/ PIN TRANSITION DETECTOR T2EX PIN EXEN2 Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) OSC PIN TR2 1999 Oct 27 89C51/89C52/89C54/89C58 TL2 TH2 (8-BITS) (8-BITS) CONTROL TR2 RELOAD RCAP2L RCAP2H CONTROL (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 ...
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... Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. 1999 Oct 27 89C51/89C52/89C54/89C58 TL2 TH2 (8-bits) (8-bits) ...
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... NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 1999 Oct 27 89C51/89C52/89C54/89C58 If Timer 2 is being clocked internally , the baud rate is: f OSC Baud Rate + [65536 * (RCAP2H, RCAP2L)]] ...
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... Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 1999 Oct 27 89C51/89C52/89C54/89C58 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires bit 0 and it ignores bit 1 ...
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... Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: *SMOD0 is located at PCON6. **f = oscillator frequency OSC 1999 Oct 27 89C51/89C52/89C54/89C58 SM2 REN TB8 RB8 ...
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... INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 9. UART Multiprocessor Communication, Automatic Address Recognition 1999 Oct 27 89C51/89C52/89C54/89C58 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash Interrupt Priority Structure The 89C51/89C52/89C54/89C58 have a 6-source four-level interrupt structure. There are 3 SFRs associated with the four-level interrupt. They are the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible ...
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... Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. 1999 Oct 27 89C51/89C52/89C54/89C58 PT2 PS PT1 PX1 Figure 11. IP Registers ...
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... The GF0 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. 1999 Oct 27 89C51/89C52/89C54/89C58 DPS BIT0 AUXR1 1 0 – ...
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... Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect ELECTRICAL CHARACTERISTICS + – +85 C amb SYMBOL PARAMETER 1/t Oscillator frequency: U (33MHz) CLCL 1999 Oct 27 89C51/89C52/89C54/89C58 RATING 0 to +70 or –40 to +85 –65 to +150 0 to +13.0 –0.5 to +6.5 15 1.5 CLOCK FREQUENCY RANGE –f MIN ...
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... ALE is tested except when ALE is off then V OH1 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except pF). 1999 Oct 27 89C51/89C52/89C54/89C58 = TEST CONDITIONS 4.5 V < V < 5 ...
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... Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are guaranteed to operate down to 0 Hz. 1999 Oct 27 89C51/89C52/89C54/89C58 10 ...
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... ALE PSEN t LLWL RD t LLAX t AVLL A0–A7 PORT 0 FROM RI OR DPL t AVWL PORT 2 1999 Oct 27 89C51/89C52/89C54/89C58 P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: t AVLL t LLPL t LLPL t PLPH ...
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... ALE t XLXL CLOCK t QVXH OUTPUT DATA 0 WRITE TO SBUF t XHDV INPUT DATA VALID CLEAR 0.45V 1999 Oct 27 89C51/89C52/89C54/89C58 t WHLH t WLWH t t WHQX QVWX t QVWH DATA OUT P2.0–P2.7 OR A8–A15 FROM DPF Figure 16. External Data Memory Write Cycle XHQX ...
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... I (mA Valid only within frequency specifications of the device under test 1999 Oct 27 89C51/89C52/89C54/89C58 V +0.1V LOAD V LOAD V –0.1V LOAD NOTE: For timing purposes, a port is no longer floating when a 100mV change from max for a logic ‘0’. load voltage occurs, and begins to float when a 100mV change from the loaded ...
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... V CC RST (NC) XTAL2 CLOCK SIGNAL XTAL1 V SS Figure 22. I Test Condition, Active Mode CC All other pins are disconnected V CC 0.45V Figure 24. Clock Signal Waveform for I Figure 25. I 1999 Oct 27 89C51/89C52/89C54/89C58 (NC) CLOCK SIGNAL SU00719 Figure 23. I –0.5 0.7V CC 0.2V – ...
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... The security feature protects against software piracy and prevents the contents of the FLASH from being read. The Security Lock bits are located in FLASH. The 89C51/89C52/89C54/89C58 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 8). Unlike the ROM and OTP versions, the security lock bits are independent ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash PLCC44: plastic leaded chip carrier; 44 leads 1999 Oct 27 89C51/89C52/89C54/89C58 28 Product specification SOT187-2 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash DIP40: plastic dual in-line package; 40 leads (600 mil) 1999 Oct 27 89C51/89C52/89C54/89C58 29 Product specification SOT129-1 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash QFP44: plastic quad flat package; 44 leads 1999 Oct 27 89C51/89C52/89C54/89C58 30 Product specification ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 1999 Oct 27 89C51/89C52/89C54/89C58 NOTES 31 Product specification ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 1999 Oct 27 89C51/89C52/89C54/89C58 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 32 Product specification All rights reserved. Printed in U.S.A. Date of release: 10-99 9397–750–06613 ...