LM3528TMX National Semiconductor, LM3528TMX Datasheet - Page 15

• Manufacturer Part Number: LM3528TMX
• Description: LM3528 High Efficiency, Multi Display LED Driver with 128 Exponential Dimming Steps and Integrated OLED Power Supply in a 1.2mm - 1.6mm uSMD Package; Package: MICRO SMD; No of Pins: 12; Qty per Container: 3000; Container: Reel
• Manufacturer: National Semiconductor

FB
room at the input to the current sinks for proper current
regulation.
In the instance when there are unequal numbers of LEDs or
unequal currents from string to string, the string with the high-
est voltage will be the regulation point.
UNISON/NON-UNISON MODE
Within White LED mode there are two separate modes of op-
eration, Unison and Non-Unison. Non-Unison mode provides
for independent current regulation, while Unison mode gives
up independent regulation for more accurate matching be-
tween LED strings. When in Non-Unison mode the LED cur-
rents I
registers BMAIN and BSUB respectively (see Brightness
Registers BMAIN and BSUB section). When in Unison mode
BSUB is disabled and both I
BMAIN only.
START-UP
The LM3528 features an internal soft-start, preventing large
inrush currents during start-up that can cause excessive volt-
age ripple on the input. For the typical application circuits
when the device is brought out of shutdown the average input
current ramps from zero to 450mA in approximately 1.2ms.
See Start Up Plots in the Typical Performance Characteris-
tics.
OLED MODE
When the LM3528 is configured for a single White LED bias
+ OLED display bias (OLED mode), the non-inverting input of
the error amplifier is connected to the internal 1.21V reference
via MUX S2. MUX S1 switches SUB/FB to the inverting input
of the error amplifier while disconnecting the internal current
sink at SUB/FB. The voltage at MAIN is not regulated in OLED
mode so when the application requires white LED + OLED
panel biasing, ensure that at least 300mV of headroom is
maintained at MAIN to guarantee proper regulation of I
(see the Typical Performance Characteristics for a plot of
I
PEAK CURRENT LIMIT
The LM3528’s boost converter has a peak current limit for the
internal power switch of 770mA typical (650mA minimum).
When the peak switch current reaches the current limit the
duty cycle is terminated resulting in a limit on the maximum
output current and thus the maximum output power the
LM3528 can deliver. Calculate the maximum LED current as
a function of V
ƒ
be found in the efficiency and I
formance Characteristics.
OVER VOLTAGE PROTECTION
The LM3528's output voltage (V
by the Output Over-Voltage Protection Threshold (V
21.2V (min). In White LED mode during output open circuit
LED
SW
are at least 500mV, thus providing enough voltage head-
vs Current Source Headroom Voltage)
= 1.27MHz. Typical values for efficiency and I
MAIN
and I
IN
, V
SUB/FB
OUT
, L and I
are independently controlled via
MAIN
PEAK
PEAK
OUT
and I
) is limited on the high end
curves in the Typical Per-
as:
SUB/FB
are controlled via
PEAK
OVP
MAIN
can
) of
.
15
conditions the output voltage will rise to the over voltage pro-
tection threshold. When this happens the controller will stop
switching causing V
drops below 19.7V (min) the device will resume switching. If
the device remains in an over voltage condition the LM3528
will repeat the cycle causing the output to cycle between the
high and low OVP thresholds. See waveform for OVP condi-
tion in the Typical Performance Characteristics.
OUTPUT CURRENT ACCURACY AND CURRENT
MATCHING
The LM3528 provides both precise current accuracy (% error
from ideal value) and accurate current matching between the
MAIN and SUB/FB current sinks. Two modes of operation af-
fect the current matching between I
mode (Non-Unison mode) is set by writing a 0 to bit 2 of the
General Purpose register (UNI bit). Non-Unison mode allows
for independent programming of I
BMAIN and BSUB respectively. In this mode typical matching
between current sinks is 1%.
Writing a 1 to UNI configures the device for Unison mode. In
Unison mode, BSUB is disabled and I
controlled via register BMAIN. In this mode typical matching
is 0.15%.
LIGHT LOAD OPERATION
The LM3528 boost converter operates in three modes; con-
tinuous conduction, discontinuous conduction, and skip mode
operation. Under heavy loads when the inductor current does
not reach zero before the end of the switching period the de-
vice switches at a constant frequency. As the output current
decreases and the inductor current reaches zero before the
end of the switching cycle, the device operates in discontin-
uous conduction. At very light loads the LM3528 will enter skip
mode operation causing the switching period to lengthen and
the device to only switch as required to maintain regulation at
the output.
HARDWARE ENABLE/PATTERN GENERATOR/
GENERAL PURPOSE I/O (HWEN/PGEN/GPIO)
HWEN/PGEN/GPIO can be configured for three different
modes of operation; Hardware Enable, Pattern Generation,
and General Purpose I/O. Register HPG at address 0x80
controls the functionality of this pin (see Table 6).
HARDWARE ENABLE (HWEN)
On initial power-up HWEN/PGEN/GPIO defaults to the Hard-
ware Enable (HWEN) state. In this mode HWEN/PGEN/GPIO
is an active high open-drain input enable to the device. When
in HWEN mode HWEN/PGEN/GPIO must be pulled up to at
least 0.7 × VIO to enable the device. In HWEN mode pulling
HWEN/PGEN/GPIO below 0.36 × VIO will shutdown the
LM3528, resetting all registers, and forcing MAIN, SUB/FB,
and SW high impedance. Bit 0 of the HPG register controls
the HWEN function. Writing a ‘0’ to this bit enables the HWEN
mode. Writing a ‘1’ to this bit disables the HWEN mode and
allows selection between the other two modes.
PATTERN GENERATOR (PGEN)
With bit 0 of the HPG register set to 1, HWEN/PGEN/GPIO
can be programmed as an open drain Pattern Generator Out-
put (PGEN). In PGEN mode a 32 bit pattern is output at
HWEN/PGEN/GPIO. This pattern can be programmed to re-
peat itself at 4 different frequencies and 6 different duty
cycles. The arbitrary pattern is programmed into four 8 bit
registers; PGEN0 (address 0x90), PGEN1 (address 0x91),
PGEN2 (address 0x92), and PGEN3 (address 0x93) (see
OUT
to droop. When the output voltage
MAIN
MAIN
MAIN
and I
and I
and I
SUB/FB
SUB/FB
SUB/FB
via registers
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. The first
are both