IDT72201L15J IDT, Integrated Device Technology Inc, IDT72201L15J Datasheet - Page 11

• Manufacturer Part Number: IDT72201L15J
• Description: IC FIFO 256X9 SYNC 15NS 32-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72201L15J

• Function: Synchronous
• Memory Size: 2.3K (256 x 9)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Configuration: Dual
• Density: 2.25Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 256x9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72201L15J

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NOTES:
1. n = PAE offset.
2. t
3. If a read is performed on this rising edge of the Read Clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
(If Applicable)
(If Applicable)
NOTES:
1. m = PAF offset .
2. 64-m words in FIFO for IDT72421, 256-m words for IDT72201, 512-m words for IDT72211, 1,024-m words for IDT72221, 2,048-m words for IDT72231, 4,096-m words for IDT72241,
3. t
4. If a write is performed on this rising edge of the Write Clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
the rising edge of RCLK is less than t
SKEW2
and 8,192-m words for IDT72251.
the rising edge of WCLK is less than t
SKEW2
WEN2
WCLK
WEN2
WEN1
WCLK
RCLK
REN1,
REN2
WEN1
RCLK
REN2
REN1,
is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and
PAE
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
PAF
n words in FIFO
t
CLKH
t
CLKH
SKEW2
SKEW2
Full - (m+1) words in FIFO
, then PAE may not change state until the next RCLK rising edge.
t
t
t
t
SKEW2
ENS
t
ENS
ENS
, then PAF may not change state until the next WCLK rising edge.
ENS
t
t
CLKL
CLKL
(1)
(2)
Figure 11. Programmable Empty Flag Timing
Figure 10. Programmable Full Flag Timing
t
t
ENH
ENH
t
t
ENH
ENH
t
PAE
(1)
11
(4)
t
PAF
t
ENS
n+1 words in FIFO
t
ENS
Full - m words in FIFO
COMMERCIAL AND INDUSTRIAL
t
ENH
t
SKEW2
t
ENH
TEMPERATURE RANGES
(3)
(2)
OCTOBER 22, 2008
(3)
t
PAF
t
PAE
2655 drw 12
2655 drw 13