LM3S328-IRN20-A0T Luminary Micro, Inc., LM3S328-IRN20-A0T Datasheet - Page 58

• Manufacturer Part Number: LM3S328-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
Figure 6-2. Main Clock Tree
6.1.4.2
6.1.4.3
6.1.4.4
58
a. These are bit fields within the Run-Mode Clock Configuration (RCC) register.
OSC1
OSC2
PLL Frequency Configuration
The user does not have direct control over the PLL frequency, but is required to match the external
crystal used to an internal PLL-Crystal table. This table is used to create the best fit for PLL
parameters to the crystal chosen. Not all crystals result in the PLL operating at exactly 200 MHz,
though the frequency is within
Translation (PLLCFG) register (see page 86).
Table 6-4 on page 85 describes the available crystal choices and default programming of the
PLLCFG register. The crystal number is written into the XTAL field of the Run-Mode Clock
Configuration (RCC) register (see page 82). Any time the XTAL field changes, a read of the
internal table is performed to get the correct value. Table 6-4 on page 85 describes the available
crystal choices and default programming values.
PLL Modes
The PLL has two modes of operation: Normal and Power-Down
The modes are programmed using the RCC register fields as shown in Table 6-4 on page 85.
PLL Operation
If the PLL configuration is changed, the PLL output is not stable for a period of time (PLL
T
The PLL is changed by one of the following:
A counter is defined to measure the T
oscillator. The range of the main oscillator has been taken into account and the down counter is
set to 0x1200 (that is, ~600
keep the PLL from being used as a system clock until the T
two changes above. It is the user's responsibility to have a stable clock source (like the main
oscillator) before the RCC register is switched to use the PLL.
1-8 MHz
Internal
15 MHz
READY
Main
Osc
Osc
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the
output.
Change to the XTAL value in the RCC register (see page 82)—writes of the same value do not
cause a relock.
Change in the PLL from Power-Down to Normal mode.
=0.5 ms) and during this time, the PLL is not usable as a clock reference.
÷4
OSCSRC
µs
a
±
at a 8.192-MHz external oscillator clock). Hardware is provided to
1%. The result of the lookup is kept in the XTAL to PLL
PWRDN
Preliminary
(200 MHz
XTAL
OEN
output )
PLL
READY
a
a
a
requirement. The counter is clocked by the main
BYPASS
a
READY
(16.667 MHz output )
Constant
SYSDIV
Divide
condition is met after one of the
a
USESYSDIV
a
April 27, 2007
ADC Clock
System Clock