LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 243
LM3S600-IQN20-A0T
Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600-IQN20-A0T.pdf
(378 pages)
- Current page: 243 of 378
- Download datasheet (4Mb)
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD4
Type RO, reset 0x0000.0000
October 01, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
RO
RO
30
14
0
0
reserved
Name
PID5
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
26
10
0
0
0x0000
Reset
0x00
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
PID5
LM3S600 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
243
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