AN1058 Freescale Semiconductor / Motorola, AN1058 Datasheet - Page 12

• Manufacturer Part Number: AN1058
• Description: Reducing A/D Errors in Microcontroller Applications
• Manufacturer: Freescale Semiconductor / Motorola

Application Note
A Specific MCU with ADC
12
Other factors involving a more specific ADC system contribute to
reduced ADC performance. Thus, this discussion will focus on the ADC
system found on the Motorola M68HC11 Family of MCUs.
A unique implementation of an SAC, the standard M68HC11 (2-MHz
bus) ADC provides a 16- s 8-bit A/D conversion with the convenience of
an on-chip MCU peripheral. The ADC is a charge-redistribution SAC.
The digital-to-analog converter (DAC) is implemented with capacitors
rather than the usual R-2R silicon-chromium (SiCr) thin-film resistors.
Although the SiCr resistor has the advantage over the commonly used
diffused resistor in improved temperature stability and tracking, laser
trimming is necessary to obtain ADC accuracies compatible with even
medium-resolution converters. Processing this R-2R ladder presents a
challenge since trimming one resistor in the network will change the
current in the previously trimmed bit, requiring an iterative trimming
process. Furthermore, the R-2R ladder requires careful control of the ON
resistance in the MOS switches because the switches also determine
the current flow through the R-2R network. The M68HC11 capacitive
DAC avoids these shortcomings. The charge-redistribution method is
easily fabricated using poly-poly capacitors. No trimming of the poly
capacitors or MOS switches is required to obtain medium-resolution
accuracies. As an added benefit, a sample-hold function, which extends
the effective conversion bandwidth of the ADC, is an inherent by-product
of the redistribution technique.
The internal operatives of the M68HC11 converter are relevant to
preventing or reducing ADC errors. For converters using SiCr R-2R
ladders, the impact of parametric phenomena may be different than for
the M68HC11. It is necessary to understand the nature and
implementation of the ADC to realize the highest performance from it. To
understand the M68HC11 conversion process, a 2-bit example is
presented (see
of three operations. In the sample mode (see
is connected to V
input voltage, V
proportional to the input voltage. In the hold mode (see
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Figure
X
, resulting in a stored charge on the top plate that is
L
(0 volts), and the bottom plates are connected to the
5). A conversion is accomplished by a sequence
Figure
5(a)), the top plate
Figure
MOTOROLA
5(b)), the
AN1058