IDT72225LB15J8 IDT, Integrated Device Technology Inc, IDT72225LB15J8 Datasheet - Page 15

• Manufacturer Part Number: IDT72225LB15J8
• Description: IC FIFO 1024X18 SYNC 15NS 68PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72225LB15J8

• Function: Synchronous
• Memory Size: 18.4K (1K x 18)
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Configuration: Dual
• Density: 18Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 1Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72225LB15J8

DEPTH EXPANSION CONFIGURATION —
(WITH PROGRAMMABLE FLAGS)
512/1,024/2,048/4,096 words of buffering. Figure 21 shows Depth Expansion
using three IDT72205LB/72215LB/72225LB/72235LB/72245LBs. Maximum
depth is limited only by signal loading. Follow these steps:
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
WRITE ENABLE
These devices can easily be adapted to applications requiring more than 256/
1. The first device must be designated by grounding the First Load (FL)
2. All other devices must have FL in the HIGH state.
WRITE CLOCK
control input.
DATA IN
RESET
LOAD
Figure 21. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
FIRST LOAD (
Vcc
Vcc
)
Dn
WCLK
WCLK
Dn
Dn
WCLK
72205LB
72215LB
72225LB
72235LB
72245LB
72205LB
72215LB
72225LB
72235LB
72245LB
72205LB
72215LB
72225LB
72235LB
72245LB
IDT
IDT
IDT
RCLK
RCLK
RCLK
Qn
Qn
Qn
15
TM
3. The Write Expansion Out (WXO) pin of each device must be tied to
4. The Read Expansion Out (RXO) pin of each device must be tied to the
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in this Depth Expansion
7. EF, FF, PAE, and PAF are created with composite flags by ORing
the Write Expansion In (WXI) pin of the next device. See Figure 21.
Read Expansion In (RXI) pin of the next device. See Figure 21.
Configuration.
together every respective flags for monitoring. The composite PAE
and PAF flags are not precise.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
READ CLOCK
READ ENABLE
DATA OUT
OUTPUT ENABLE
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