DS1236 DALLAS, DS1236 Datasheet - Page 4

• Manufacturer Part Number: DS1236
• Description: MicroManager Chip
• Manufacturer: DALLAS

NON-MASKABLE INTERRUPT
The DS1236 generates a non-maskable interrupt
microprocessor. A precision comparator monitors the voltage level at the IN pin relative to a reference
generated by the internal band gap. The IN pin is a high-impedance input allowing for a user-defined
sense point. An external resistor voltage divider network (Figure 6) is used to interface with high voltage
signals. This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage
level closer to the main system power input. Since the IN trip point V
for R1 and R2 can be determined by the equation as shown in Figure 6. Proper operation of the DS1236
requires that the voltage at the IN pin be limited to V
supply being monitored (V
this equation is to select a value for R2 high enough to keep power consumption low, and solve for R1.
The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power
supply system, maximizing the amount of time for microprocessor shutdown between
When the supply being monitored decays to the voltage sense point, the DS1236 pulses the
to the active state for a minimum of 200 s. The
domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33 s/cycle). Three consecutive samplings of
out-of-tolerance supply (below V
must be below the voltage sense point for approximately 100 s or the comparator will reset. In this way,
power supply noise is removed from the monitoring function, preventing false trips. During a power-up,
any IN pin levels below V
any potential
Removal of an active low level on the
is less than V
signal during power-up results in an
on the relative voltage relationship between V
is tied to ground during power-up, the internal time-out will result in a pulse of 200 s minimum to 500
power-up. Note that a fast slewing power supply may cause the
power-up. This is of no consequence, however, since an RST will be active.
RST
s maximum. In contrast, if the IN pin is tied to V
.
TP
NMI
) or by the subsequent rise of the IN pin above V
pulse will not be initiated until V
TP
MAX
are disabled from reaching the
) can also be derived as shown in Figure 6. A simple approach to solving
SENSE
NMI
) must occur at the IN pin to activate
NMI
pulse of from 0 s minimum to 500 s maximum, depending
pin is controlled by either an internal time-out (when IN pin
CC
and the IN pin voltage. As an example, when the IN pin
4 of 19
NMI
CCO
CC
IN
. Therefore, the maximum allowable voltage at the
power-fail detection circuitry also has built-in time
during power-up,
NMI
reaches V
NMI
for early warning of power failure to a
TP
CCTP
pin until V
. The initiation and removal of the
.
NMI
TP
NMI
is 2.54 volts, the proper values
to be virtually nonexistent on
CC
NMI
will not produce a pulse on
rises to V
. Therefore, the supply
NMI
CCTP
. As a result,
and RST or
NMI
DS1236
output
NMI