DS17485 Dallas, DS17485 Datasheet - Page 22

• Manufacturer Part Number: DS17485
• Description: (DS17486 / DS17487) 3V/5V Real-Time Clock
• Manufacturer: Dallas

DS17485/DS17487
EXTENDED CONTROL REGISTER 4B
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ABE
E32k
CS
RCE
PRS
RIE
WIE
KSE
ABE – Auxiliary Battery Enable. This bit when written to a logic 1 enables the V
pin for extended
BAUX
functions.
E32k – Enable 32.768kHz Output. This bit when written to a logic 1 enables the 32.768kHz oscillator
frequency to be output on the SQW pin. E32k is set to a 1 when V
is powered up.
CC
CS – Crystal Select. When CS is set to a 0, the oscillator is configured for operation with a crystal that
has a 6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is
disabled in the DS17487 module and should be set to CS = 0.
RCE – RAM Clear Enable. When set to a 1, this bit enables a low level on
to clear all 114 bytes
RCLR
of user RAM. When RCE = 0,
and the RAM clear function are disabled.
RCLR
PRS – PAB Reset Select. When set to a 0, the
pin is set high-z when the DS17485 goes into power
PWR
fail. When set to a 1, the
pin remains active upon entering power fail.
PWR
RIE – RAM Clear Interrupt Enable. When RIE is set to a 1, the
pin is driven low when a RAM
IRQ
clear function is completed.
WIE – Wake-up Alarm Interrupt Enable. When V
voltage is absent and WIE is set to a 1, the
PWR
CC
pin is driven active low when a wake-up condition occurs, causing the WF bit to be set to 1. When V
is
CC
then applied, the
pin is also driven low. If WIE is set while system power is applied, both
and
IRQ
IRQ
are driven low in response to WF being set to 1. When WIE is cleared to a 0, the WF bit has no
PWR
affect on the
or
pins.
PWR
IRQ
KSE – Kickstart Interrupt Enable. When V
voltage is absent and KSE is set to a 1, the
pin is
PWR
CC
driven active low when a kickstart condition occurs (
pulsed low), causing the KF bit to be set to 1.
KS
When V
is then applied, the
pin is also driven low. If KSE is set to 1 while system power is
IRQ
CC
applied, both
and
are driven low in response to KF being set to 1. When KSE is cleared to a 0,
IRQ
PWR
the KF bit has no affect on the
or
pins.
PWR
IRQ
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