DS1851 Dallas Semiconducotr, DS1851 Datasheet - Page 17

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DS1851

Manufacturer Part Number
DS1851
Description
Dual Temperature-Controlled NV Digital-to-Analog Converters
Manufacturer
Dallas Semiconducotr
Datasheet
www.DataSheet4U.com
DataSheet U .com
NOTES:
1. All voltages are referenced to ground.
2. A fast-mode device can be used in a standard-mode system, but the requirement t
3. After this period, the first clock pulse is generated.
4. The maximum t
5. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
6. C
7. EEPROM-write begins after a STOP condition occurs.
8. Measured with SDA = SCL = V
9. Valid at 25°C only.
10. With V
11. 0.8% is equivalent to 2 LSB.
4
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
SCL signal.
VI
B
H MIN
- total capacitance of one bus line in pF, timing referenced to (0.9)(V
rc
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
= V
CC
-1.25 and V
HD:DAT
has only to be met if the device does not stretch the LOW period (t
RMAX
rg
= 1.25 + GND.
+ t
rc
SU:DAT
= V
CC
= 1000 + 250 = 1250ns before the SCL line is released.
, and V
17 of 17
rg
= GND. The outputs OutV and OutG are left open.
CC
) and (0.1)(V
SU:DAT
CC
> 250ns must
LOW
).
) of the
DS1851

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