DS2148 Dallas Semiconducotr, DS2148 Datasheet - Page 11

• Manufacturer Part Number: DS2148
• Description: 5V E1/T1/J1 Line Interface
• Manufacturer: Dallas Semiconducotr

PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name,
DS2148T Pin Numbering) Table 4-2b
ACRONYM
D0 / AD0
D7 / AD7
BPCLK
HRST*
MCLK
PBEO
PBTS
BIS0/
INT*
BIS1
ALE
(AS)
CS*
NA
A0
A4
To
To
PIN
32/
11
33
19
12
29
23
30
24
44
31
to
to
7
4
1
-
I/O
I/O
O
O
O
I
I
I
I
I
I
I
I
DESCRIPTION
Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =
1), serves as the address bus. In multiplexed bus operation (BIS1 =
0, BIS0 = 0), these pins are not used and should be tied low.
Address Latch Enable (Address Strobe). When using the parallel
port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to
demultiplex the bus on a positive-going edge. In nonmultiplexed bus
mode (BIS0 = 1), should be tied low.
Bus Interface Select Bits 0 & 1. Used to select bus interface option.
See Table 4-1 for details.
Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
Chip Select. Must be low to read or write to the device. CS* is an
active low signal.
Data Bus/Address/Data Bus. In non-multiplexed bus operation
(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus
operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed
address/data bus.
Hardware Reset. Bringing HRST* low will reset the DS2148
setting all control bits to their default state of all zeros.
Interrupt [INT*] pin 23. Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
See Note 1 on clock accuracy at the end of this table.
Not Assigned. Should be tied low.
PRBS Bit Error Output. The receiver will constantly search for a
2
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
Parallel Bus Type Select. When using the parallel port (BIS1 = 0),
set high to select Motorola bus timing, set low to select Intel bus
timing. This pin controls the function of the RD*(DS*), ALE(AS),
and WR*(R/W*) pins. If PBTS = 1 and BIS1 = 0, then these pins
assume the Motorola function listed in parenthesis (). In serial port
mode, this pin should be tied low.
15
-1 or a 2
20
-1 PRBS depending on the ETS bit setting (CCR1.7).
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