DS2480 Dallas Semiconducotr, DS2480 Datasheet - Page 14
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DS2480
Manufacturer Part Number
DS2480
Description
Serial 1.Wire Line Driver
Manufacturer
Dallas Semiconducotr
Datasheet
1.DS2480.pdf
(26 pages)
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The idle time following the Reset/Presence Detect
sequence depends on the serial communication speed
and the host’s response time.
A Write 1 and Read Data time slot is comprised of the
segments t
slots, after the write 1 low time t
DS2480 waits for the duration of the data sample offset
and then samples the voltage at the 1–Wire bus to read
the response. After this, the waiting time t
expire before the time slot is complete. A Write 0 time
slot only consists of the two segments t
If the network is large or heavily loaded, one should
select flexible speed and extend t
Since a large or heavily loaded network needs more
WRITE 1 AND READ DATA TIME SLOT Figure 6b
WRITE 0 TIME SLOT Figure 6c
*In a 5V environment ( 1V, full temperature range) the tolerance of the internal time base of 1–Wire slave devices is
much narrower than what it is when operated at the minimum voltage of 2.8V. Therefore, the timing generated by the
DS2480 is in compliance with the requirements of all MicroLAN–compatible 1–Wire devices.
DS2480
042498 14/26
s to allow the 1–Wire bus to completely discharge.
Overdrive
Regular
Flexible
Speed
5V
0V
Overdrive
Regular
Flexible
Speed
LOW1
5V
0V
t
, t
LOW1
DSO
and t
HIGH
8 to 15 s
t
DSO
t
LOW1
8 s
1 s
. During write 1 time
LOW1
LOW1
TIME SLOT DURATION t
SAMPLING
LOW0
t
to more than 8
LOW0
57 s
57 s
7 s
TIME SLOT DURATION t
is over, the
t
HIGH1
LOW0
and t
*
REC0
must
3 to 10 s
.
t
3 s
1 s
DSO
SLOT
t
HIGH1
time to recharge, it is also recommended to delay sam-
pling the bus for reading. A higher value for t
increase the voltage margin and also provide extra
energy to the slave devices when generating a long
series of write 0 time slots. However, the total of t
t
device responding may have stopped pulling the bus
low when transmitting a logic 0.
The idle time between time slots within a byte or during a
12–bit sequence while the Search Accelerator is on is
zero. Between bytes, 12–bit search sequences and
single bits the idle time depends on the RS232 data rate
and the host’s response time. The response byte is sent
to the host as soon as the last time slot of a byte, 12–bit
sequence or the command is completed.
DSO
SLOT
should not exceed 22 s*. Otherwise the slave
3 to 10 s
t
REC0
3 s
3 s
t
RECO
t
49 s
49 s
HIGH1
8 s
IDLE
TIME
TIME
IDLE
NEXT
T.S.
NEXT
T.S.
60 to 67 s
t
60 to 74 s
60 s
10 s
SLOT
t
60 s
10 s
SLOT
*
*
DSO
LOW1
will
+