AN1525 STMicroelectronics, AN1525 Datasheet - Page 5

• Manufacturer Part Number: AN1525
• Description: I2C COMMUNICATION BETWEEN ST52X520 AND EEPROM
• Manufacturer: STMicroelectronics

AN1525 - APPLICATION NOTE
Figure 7. PROGRAM FLAG DEFINITION
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The use of a register with various flags is necessary in this program, seeing that within a sole routine (I
C
interrupt) the program manages all phases of sequential writing, random reading and all interrupt events
generated during the various steps of every phase (see Figure 8).
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The program flow begins by enabling the interrupt of the I
C peripheral and afterwards enables the pe-
ripheral iteself (IrqMask_0, I2C_EN controls). The program flow is interrupted immediately after the Wait0
block. Once the pushbutton is pressed, the status of bit b0 of the FLAG register is inverted. This occurs
via an XOR operation on the b0 bit of the FLAG register. Initially, as FLAG = 1, b0 will be reset to ‘0’. This
last operation is performed by the external interrupt routine, which sets bit 7 of the FLAG register to ‘1’. In
this manner, the External Interrupt Routine will be executed again only at the end of reading or writing to
the memory.
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After exiting the routine via the Ret10 control, the START condition will be activated through the I
C pe-
ripheral of the ST52x520 micocontroller and bit 6 will be set to ‘1’ in the FLAG register. This flag bit is nec-
essary since the START condition begins at the Main Program level, while the communication
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management occurs after each event generated by the I
C interrupt routine.
In the Norm_Op block, a code can be inserted to perform operations while the microcontroller communi-
cates with the memory. Finally, the PB_0 block resets the value of port B to 0. Figure 8 represents the
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sequence to be followed to receive and transmit data to an I
C peripheral, configuring the ST52x520 mi-
crocontroller as master (receiver and transmitter) with the addressing mode of 7 bits (refer to the
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ST52x520 datasheet for the complete diagram of the sequences, relative to the I
C peripheral of the mi-
crocontroller).
Figure 8. 7 BIT MASTER TRANSFER SEQUENCING
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