DS2703 Dallas Semiconductor, DS2703 Datasheet - Page 6

no-image

DS2703

Manufacturer Part Number
DS2703
Description
SHA-1 Battery Pack Authentication IC
Manufacturer
Dallas Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS2703G+T&R
Manufacturer:
MAXIM/美信
Quantity:
20 000
Table 1. Variable Initiation
The 160-bit MAC is computed per FIPS 180, including the addition of constants H0-H4. Adding H0-H4 is necessary
only to maintain compliance with FIPS 180. The computed MAC is held in the A-E register memory and then
returned as a 160-bit serial stream, beginning with the least significant bit of variable A.
Table 2. Message Authentication Code (MAC) Return Format
SHA-1 HASH ALGORITHM
General Definitions:
This description of the SHA computation is adapted from the Secure Hash Standard SHA-1 document. The
algorithm takes as its input data 16, 32-bit words M
tables. The SHA computation involves six 32-bit word variables labeled A, B, C, D, E, and TMP, five 32-bit word
constants labeled H0, H1, H2, H3, and H4, a sequence of eighty 32-bit words called W
eighty 32-bit words called K
the SHA computation are arithmetic addition without carry ("+"), logical inversion or 1's complement ("\"), logical
XOR ("Å"), logical AND ("^"), logical OR ("v"), concatenation of 32-bit values (“|”), assignment (":=") and circular
shifting within a 32-bit word. The expression S
being a 32-bit word.
The function f
The sequence K
K
The sequence W
W
f
t
t
(B,C,D) =
t
:=
:=
A
B
C
D
E
A[31:24]
B[31:24]
C[31:24]
D[31:24]
E[31:24]
=
=
=
t
is defined as follows:
(B^C)v((B\)^D)
B Å C Å D
(B^C)v(B^D)v(C^D)
B Å C Å D
5A827999h
6ED9EBA1h
8F1BBCDCh
CA62C1D6h
M
S
t
1
t
t
(0 ≤ t ≤ 79) is defined as follows:
(W
(0 ≤ t ≤ 79) is defined as follows:
(see table, FIPS-180 compliant input block)
[31:0]
EFh
C3h
67h
98h
10h
t-3
Å W
t
t-8
A[23:16]
B[23:16]
C[23:16]
D[23:16]
E[23:16]
(0 ≤ t ≤ 79), and a Boolean function f
Å W
[23:16]
CDh
BAh
D2h
t-14
45h
32h
Å W
(0 ≤ t ≤ 19)
(20 ≤ t ≤ 39)
(40 ≤ t ≤ 59)
(60 ≤ t ≤ 79)
(0 ≤ t ≤ 19)
(20 ≤ t ≤ 39)
(40 ≤ t ≤ 59)
(60 ≤ t ≤ 79)
t-16
) (16 ≤ t ≤ 79)
A[15:8]
B[15:8]
C[15:8]
D[15:8]
n
E[15:8]
(X) represents a circular shift of X by n positions to the left, with X
[15:8]
DCh
ABh
E1h
23h
54h
t
6 of 20
(0 ≤ t ≤ 15) as shown in the SHA-1 Input Message Format
[7:0]
FEh
F0h
01h
89h
76h
(0 ≤ t ≤ 15)
A[7:0]
B[7:0]
C[7:0]
D[7:0]
E[7:0]
t
(B,C,D) (0 ≤ t ≤ 79). The operations required for
t
(0 ≤ t ≤ 79), a sequence of

Related parts for DS2703