DS2745 Maxim Integrated Products, DS2745 Datasheet - Page 13

• Manufacturer Part Number: DS2745
• Description: Low-Cost I2C Battery Monitor
• Manufacturer: Maxim Integrated Products

Read/Write Bit
The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0
selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a read
transaction, with the following bytes being read from the stave by the master.
Bus Timing
The DS2745 is compatible with any bus timing up to 400kHz. No special configuration is required to operate at any
speed.
2-Wire Command Protocols
The command protocols involve several transaction formats. The simplest format consists of the master writing the
START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2745. More
complex formats such as the Write Data, Read Data and Function command protocols write data, read data and
execute device specific operations. All bytes in each command format require the slave or host to return an
Acknowledge bit before continuing with the next byte. Each function command definition outlines the required
transaction format. The following key applies to the transaction formats.
Table 3. 2-Wire Protocol Key
Basic Transaction Formats
Write:
A write transaction transfers one or more data bytes to the DS2745. The data transfer begins at the memory
address supplied in the MAddr byte. Control of the SDA signal is retained by the master throughout the transaction,
except for the Acknowledge cycles.
Read:
A read transaction transfers one or more bytes from the DS2745. Read transactions are composed of two parts, a
write portion followed by a read portion, and is therefore inherently longer than a write transaction. The write portion
communicates the starting point for the read operation. The read portion follows immediately, beginning with a
Repeated START, Slave Address with R/W set to a 1. Control of SDA is assumed by the DS2745 beginning with
the Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2745 throughout the
transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding
to the last byte it requires with a No Acknowledge. This signals the DS2745 that control of SDA is to remain with
the master following the Acknowledge clock.
S
SAddr
FCmd
MAddr
Data
A
N
KEY
S SAddr W A MAddr A Data0 A P
S SAddr W A MAddr A Sr SAddr R A Data0 N P
START bit
Slave Address (7-bit)
Function Command byte
Memory Address byte
Data byte written by master
Acknowledge bit - Master
No Acknowledge - Master
Write Portion
DESCRIPTION
Read Portion
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Data
KEY
Sr
W
R
P
A
N
Repeated START
R/W bit = 0
R/W bit = 1
STOP bit
Data byte returned by slave
Acknowledge bitSlave
No AcknowledgeSlave
DESCRIPTION
DS2745 Low-Cost I
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2
C Battery Monitor