DS2790 Maxim Integrated Products, DS2790 Datasheet - Page 27

• Manufacturer Part Number: DS2790
• Description: Programmable 1-Cell Li-Ion Fuel Gauge and Protector
• Manufacturer: Maxim Integrated Products

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2-Wire Slave Interrupts
An interrupt is generated when any condition that sets an interrupt status register bit occurs, and the corresponding
interrupt mask bit in the 2-Wire Slave Interrupt Mask Register (TWSIM) is also set. All 2-wire interrupts are
maskable by clearing the corresponding bit in the TWSIM. Upon system reset, all 2-wire interrupt mask bits are
cleared automatically. The interrupt status register is 2 bytes in length and is readable and writeable by the
MAXQ20 core.
Like the high level interrupt status register in the core, when the TWSINT register is read, the state of the interrupt
status bits are returned but not altered. Edge triggered interrupt status bits are cleared by writing a ‘0’ to their
location. Any attempt to write a ‘1’ is ignored. Level triggered interrupt status bits are cleared automatically after
the event that caused the interrupt to occur has ended.
Table 10. 2-Wire Slave Interrupt Sources
Transmit and Receive Data Buffers
Since multiple data bytes can be associated with a single command byte, the TWS is designed with transmit and
receive buffers to prevent data loss and reduce CPU overhead during a communication sequence. Data received
from the master is directed to an 8 byte deep receive first in, first out buffer (RXD FIFO) until read by the CPU.
Data to be transmitted by the DS2790 is stored in a separate 8-byte transmit FIFO buffer (TXD FIFO) until the
master reads it. If the RXD FIFO buffer becomes completely full or the TXD FIFO buffer becomes completely
empty during communication, the interface will begin clock extending the bus to maintain data integrity.
The CPU has access to the TXD and RXD FIFOs through the Transmit/Receive Data register (TWSTXD/RXD).
During a master read (TWS transmit) data is pushed onto the TXD FIFO by writing to the TWSTXD/RXD register.
Likewise, during a master write (TWS receive), the CPU can pull data off the RXD FIFO by reading the
TWSTXD/RXD register.
INTERRUPT
RXD_EMPTY
4
TXD_EMPTY
(TWSINT)
RXD_BYTE
RXD_FULL
TXD_BYTE
RXD_CMD
TXD_FULL
RESTART
RESTART
TIMEOUT
_WRITE
_READ
START
STOP
RXD_BYTE_MASK
TXD_BYTE_MASK
RXD_FULL_MASK
TXD_FULL_MASK
RESTART_WRITE
RXD_CMD_MASK
RESTART_READ
TIMEOUT_MASK
START_MASK
STOP_MASK
RXD_EMPTY
TXD_EMPTY
(TWSIM)
MASK
_MASK
_MASK
_MASK
_MASK
When the RXD FIFO is full.
RXD buffer is empty.
Byte moved from the incoming shift register to the RXD FIFO.
Command byte receive completed.
TXD buffer is full.
When the TXD FIFO is empty.
Byte moved from TXD FIFO to the outgoing shift register.
A start followed by the address defined in the configuration
register was recognized.
(This bit is not set during a repeated start condition.)
A repeated start followed by the address defined in the
configuration register was received with the read/write bit clear.
A repeated start followed by the address defined in the
configuration register was received with the read/write bit set.
After an address qualified Start or Restart, a STOP is recognized
on the bus.
T
event will reset the TWS interface.
TIMEOUT
or T
LOW:SEXT
DS2790 Programmable 1-Cell Li-Ion Fuel Gauge and Protector
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event recognized on the bus. Either timeout
DESCRIPTION
TRIGGER
Level
Level
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge